DCT

6:22-cv-01153

Cedar Lane Tech Inc v. Xerox Corp

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:22-cv-01153, W.D. Tex., 11/03/2022
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant maintains an established place of business in the Western District of Texas.
  • Core Dispute: Plaintiff alleges that certain unidentified Xerox products infringe three patents related to methods and modules for interfacing digital image sensors with data processing and compression hardware.
  • Technical Context: The patents address the technical challenge of efficiently transferring data from an image sensor (like in a scanner or digital camera) to a processor or compression chip, which often operate at different speeds and require data in specific formats.
  • Key Procedural History: U.S. Patent No. 8,537,242 is a divisional of the application that resulted in U.S. Patent No. 6,972,790, indicating a shared specification and priority. The complaint does not mention any other prior litigation or administrative proceedings.

Case Timeline

Date Event
1999-06-01 ’527 Patent Priority Date
2000-01-21 ’790 and ’242 Patents Priority Date
2002-10-29 ’527 Patent Issue Date
2005-12-06 ’790 Patent Issue Date
2013-09-17 ’242 Patent Issue Date
2022-11-03 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,473,527 - Module and method for interfacing analog/digital converting means and JPEG compression means (issued Oct. 29, 2002)

The Invention Explained

  • Problem Addressed: The patent’s background section describes that conventional digital imaging systems required an extra, external memory (typically RAM) to sit between the analog-to-digital (A/D) converter and the dedicated JPEG compression hardware. This external memory was needed to buffer the incoming image data and re-format it into the block-based structure (e.g., 8x8 pixels) required by the JPEG algorithm, adding cost and complexity to the device. (’527 Patent, col. 1:36-57).
  • The Patented Solution: The invention proposes an interface module that eliminates the need for this extra external memory. The module’s "read control device" reads a specific number of image lines (e.g., eight lines) from the A/D converter into an internal "memory device". This memory is sized to hold just enough data to form a compression block. An "output control device" then reads the data from this memory as a complete block and sends it directly to the JPEG compression chip. (’527 Patent, Abstract; col. 2:45-63).
  • Technical Importance: This design aimed to reduce the bill of materials and physical footprint for imaging devices like scanners by creating a more direct and efficient data pipeline between the image capture and compression stages. (’527 Patent, col. 1:53-57).

Key Claims at a Glance

  • The complaint does not identify specific asserted claims, instead incorporating by reference claim charts in an exhibit not attached to the public filing (Compl. ¶¶ 13, 15).
  • Independent claim 1, a representative claim, recites a module comprising three key elements:
    • "read control means" for reading a predetermined number of image lines from an A/D converter and generating a control signal.
    • "memory means" coupled to the read control means for storing those image lines, with a capacity matching the built-in memory of the JPEG compression device.
    • "output control means" that responds to the control signal to read an image block from the memory means and forward it to the JPEG device.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 6,972,790 - Host interface for imaging arrays (issued Dec. 6, 2005)

The Invention Explained

  • Problem Addressed: The patent explains that CMOS image sensors typically produce a continuous, high-speed stream of pixel data. This "video style output" is incompatible with standard microprocessor buses, which are designed for random data access using address and control signals. Bridging this gap required "additional glue logic" and external memory, which undermined the cost-effectiveness of using integrated CMOS sensors. (’790 Patent, col. 1:36-58).
  • The Patented Solution: The patent describes an interface, preferably integrated on the same chip as the image sensor, that acts as a bridge. This interface includes a memory (such as a FIFO buffer) to store the incoming pixel data from the sensor array. A signal generator monitors the amount of data in the memory and, once a predetermined threshold is reached, sends a signal (e.g., an interrupt) to the host processor, alerting it that data is ready to be transferred. (’790 Patent, Abstract; col. 2:4-13).
  • Technical Importance: By integrating this asynchronous buffering and signaling logic onto the sensor chip, the invention allows a microprocessor to efficiently pull data from the sensor without being locked to its high-speed clock, enabling more cost-effective and integrated "system-on-a-chip" designs. (’790 Patent, col. 1:63-66).

Key Claims at a Glance

  • The complaint does not identify specific asserted claims, incorporating them by reference from an unattached exhibit (Compl. ¶¶ 19, 24).
  • Independent claim 1, a representative claim, recites an interface comprising:
    • A "memory" for storing imaging array data at a rate determined by the sensor's clocking signals.
    • A "signal generator" for generating a signal to a processor system "in response to the quantity of data in the memory".
    • A "circuit for controlling the transfer of the data" from the memory at a rate determined by the processor system.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,537,242 - Host interface for imaging arrays (issued Sep. 17, 2013)

  • Technology Synopsis: As a divisional of the application for the ’790 Patent, this patent shares the same core technical disclosure. It describes a method and system for efficiently interfacing a continuous-output image sensor with a host processor. The solution involves buffering image data from the sensor and using a signaling mechanism, such as an interrupt or a bus request, to notify the processor to read the buffered data, thereby decoupling the sensor's timing from the processor's. (’242 Patent, Abstract; col. 1:24-42).
  • Asserted Claims: The complaint refers to an unattached exhibit for the specific asserted claims (Compl. ¶¶ 28, 33).
  • Accused Features: The complaint alleges infringement by "Exemplary Defendant Products" but provides no further specifics, incorporating them by reference from the unattached exhibit (Compl. ¶28).

III. The Accused Instrumentality

  • Product Identification: The complaint does not identify any specific accused Xerox products, methods, or services by name. It refers generally to "Exemplary Defendant Products" that are identified only in Exhibits 4, 5, and 6, which were not included with the complaint filed on the public docket (Compl. ¶¶ 13, 19, 28).
  • Functionality and Market Context: The complaint does not provide sufficient detail for analysis of the functionality or market context of the accused instrumentalities.
  • No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint alleges direct infringement of the ’527 Patent and direct and indirect infringement of the ’790 and ’242 Patents (Compl. ¶¶ 13, 19, 28). However, it does not contain narrative infringement allegations or claim charts in the body of the document. Instead, it states that infringement details are provided in Exhibits 4, 5, and 6, which are incorporated by reference but were not publicly filed (Compl. ¶¶ 16, 25, 34). As a result, a detailed analysis of the infringement allegations is not possible from the provided documents.

  • Identified Points of Contention:
    • ’527 Patent: A potential point of contention may be whether the architecture of the accused products maps onto the patent's distinct modular structure of "read control means", "memory means", and "output control means". In modern system-on-a-chip (SoC) designs, these functions may be highly integrated, raising the question of whether these claimed elements exist as structurally distinct components or their equivalents.
    • ’790 and ’242 Patents: A likely technical dispute will concern the claim limitation requiring the interface to generate a signal "in response to the quantity of data in the memory." The analysis may turn on whether the accused products' signaling is triggered by the amount of data stored (e.g., when a buffer is half-full) or by a different event, such as the receipt of a complete image line or frame, and whether such an event-based trigger meets the claim limitation.

V. Key Claim Terms for Construction

For U.S. Patent No. 6,473,527:

  • The Term: "memory means" (from claim 1)
  • Context and Importance: This term is drafted in means-plus-function format pursuant to 35 U.S.C. § 112(f). Its scope is not limitless but is confined to the structure disclosed in the specification for performing the function of "storing said predetermined number of image lines," and its equivalents. The viability of the infringement claim will depend on whether the accused memory architecture is structurally equivalent to what is disclosed in the patent.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: A party might argue the term should cover any memory structure that performs the recited storage function, regardless of its specific implementation.
    • Evidence for a Narrower Interpretation: The specification states the "memory device 24" "can save the same number of image lines as that of the memory device 271 built in the JPEG compression device 27," for example, "8 lines of image data" for an 8x8 pixel compression unit (’527 Patent, col. 3:3-8). This language could be used to argue that the scope is limited to a small, purpose-built buffer sized specifically to match the downstream compression block, not a general-purpose RAM.

For U.S. Patent No. 6,972,790:

  • The Term: "in response to the quantity of data in the memory" (from claim 1)
  • Context and Importance: This term defines the causal trigger for the "signal generator". Practitioners may focus on this term because the infringement case depends on establishing that the accused device's processor alert is caused by the amount of data accumulated in the buffer, not another factor.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: A plaintiff may argue this language covers any system where the accumulation of data is a necessary precondition for the signal, even if the direct trigger is an event like an "end-of-line" flag that coincides with a certain data quantity.
    • Evidence for a Narrower Interpretation: The specification describes a specific implementation where an "increment/decrement counter 54" tracks the number of writes and reads, and its output ("Sc") is compared to a "FIFO limit" ("S₁"). The signal is generated only when the count ("Sc") is greater than or equal to the limit ("S₁") (’790 Patent, col. 6:11-15). This suggests a direct comparison of a data quantity to a threshold, potentially narrowing the term's scope to exclude systems with purely event-based triggers.

VI. Other Allegations

  • Indirect Infringement: For the ’790 and ’242 Patents, the complaint alleges induced infringement. The factual basis asserted is that Defendant distributes "product literature and website materials" which allegedly instruct end users on how to use the accused products in an infringing manner (Compl. ¶¶ 22-23, 31-32).
  • Willful Infringement: The complaint does not use the word "willful" but lays the groundwork for a claim of post-filing willfulness for the ’790 and ’242 Patents. It alleges that service of the complaint provides "Actual Knowledge of Infringement" and that Defendant "continues to make, use, test, sell, offer for sale, market, and/or import" the products despite this knowledge (Compl. ¶¶ 21, 30).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. An Evidentiary Question of Specificity: The complaint's complete reliance on un-filed exhibits to identify the accused products and articulate its infringement theories is a central feature of the pleading. A primary question, therefore, is whether the specific, yet-to-be-disclosed allegations can be substantiated with evidence linking the functionality of any actual Xerox product to the patent claims.
  2. A Question of Structural Correspondence: For the ’527 Patent, the case may turn on whether a modern, highly integrated Xerox imaging SoC can be shown to possess the discrete, sequentially-operating "read control", "memory", and "output control" modules as recited in the claims, or their structural equivalents.
  3. A Question of Functional Causality: For the ’790 and ’242 Patents, a key issue will be one of technical operation: does the accused interface alert the processor specifically "in response to the quantity of data" in its buffer, as required by the claims, or is the alert triggered by other operational events (e.g., end-of-frame) that may not be functionally equivalent?