DCT

6:23-cv-00264

Acqis LLC v. Hon Hai Precision Industry Co Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:23-cv-00264, W.D. Tex., 07/19/2024
  • Venue Allegations: Plaintiff alleges venue is proper because Defendants are foreign corporations not resident in the United States and may therefore be sued in any judicial district. The complaint also notes that the asserted patents have been the subject of previous litigation in the Western District of Texas.
  • Core Dispute: Plaintiff alleges that smartphones, tablets, and laptops manufactured by Defendant infringe five patents related to high-speed serial data transmission technologies, particularly as implemented in industry standards like PCI Express and USB 3.x.
  • Technical Context: The technology concerns methods for serializing parallel bus transactions for high-speed, low-power data transfer using low-voltage differential signaling (LVDS), a foundational technology for modern computer input/output standards.
  • Key Procedural History: The complaint notes that two of the asserted patents (the ’140 and ’654 patents) are reissues of the same original U.S. Patent No. 6,643,777. The patents-in-suit have also been previously asserted in other cases before the Western District of Texas.

Case Timeline

Date Event
1999-05-14 Earliest Priority Date (’750, ’797, ’140, ’654 Patents)
2005-03-31 Priority Date (’769 Patent)
2007-01-01 Approx. date Hon Hai began manufacturing accused phones
2013-12-17 Issue Date (RE44,654 Patent)
2014-09-16 Issue Date (RE45,140 Patent)
2015-03-10 Issue Date (U.S. 8,977,797 Patent)
2016-12-27 Issue Date (U.S. 9,529,769 Patent)
2017-07-11 Issue Date (U.S. 9,703,750 Patent)
2024-07-19 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,703,750 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions"

  • Patent Identification: U.S. Patent No. 9,703,750, "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions," issued July 11, 2017.

The Invention Explained

  • Problem Addressed: The complaint describes the technical problem as the difficulty of using traditional parallel Peripheral Component Interconnect (PCI) bus architectures for modern, scalable interconnections. These parallel buses required a large number of signal channels and pins, making them power-inefficient, noisy, and not "cable friendly" for connecting computer modules to peripheral consoles (Compl. ¶46).
  • The Patented Solution: The invention addresses this by directly connecting a central processing unit (CPU) or a peripheral bridge to a Low Voltage Differential Signal (LVDS) channel. This channel is used to communicate the data, address, and control bits of a traditional parallel PCI bus transaction as a serial bit stream, using pairs of unidirectional lanes to transmit data in opposite directions (’750 Patent, Abstract; Compl. ¶55). This approach enables high-speed data transfer with a reduced pin count, lower power consumption, and less noise (Compl. ¶46).
  • Technical Importance: This serialization of parallel bus data over LVDS channels is described as a pioneering invention that became foundational for modern high-speed I/O standards like PCI Express (PCIe) and USB 3.x, which are ubiquitous in modern computing devices (Compl. ¶¶1, 56, 60).

Key Claims at a Glance

  • The complaint asserts at least independent method claim 50 (Compl. ¶¶122, 125).
  • The essential elements of claim 50 include:
    • Performing a method of improving external peripheral data communication of a computer.
    • Obtaining an integrated CPU and graphics controller as a single chip.
    • Connecting a first unidirectional, differential signal pair channel directly to the integrated CPU and graphics controller to output digital video data.
    • Providing a connector for external peripheral data communication.
    • Providing an LVDS channel to convey USB protocol data through the connector that uses two unidirectional, serial bit channels transmitting data in opposite directions.
  • The complaint reserves the right to assert additional claims (Compl. ¶¶124, 127).

U.S. Patent No. 8,977,797 - "Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel"

  • Patent Identification: U.S. Patent No. 8,977,797, "Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel," issued March 10, 2015.

The Invention Explained

  • Problem Addressed: The patent targets the limitations of parallel PCI communications, which were not scalable, power-efficient, or suitable for high-performance, low-pin-count connectors needed for modular computing systems (Compl. ¶46).
  • The Patented Solution: The invention describes a method for improving data throughput by mounting an integrated CPU and interface controller on a motherboard and directly connecting it to an LVDS channel. This channel, comprising two unidirectional serial paths, transmits encoded address and data bits of a PCI bus transaction. The method includes configuring the interface controller to adapt to different numbers of signal line pairs to increase throughput (’797 Patent, Abstract; Compl. ¶134). This architecture is alleged to be embodied by the PCIe standard, which uses pairs of unidirectional lanes to convey transaction layer packets (Compl. ¶¶56-59).
  • Technical Importance: The claimed method of using a configurable, serial LVDS channel for PCI transactions is alleged to be a core principle adopted by the PCIe standard, which replaced parallel PCI and became a fundamental I/O architecture in the computer industry (Compl. ¶¶56, 57).

Key Claims at a Glance

  • The complaint asserts at least independent method claim 36 (Compl. ¶¶134, 137, 140).
  • The essential elements of claim 36 include:
    • Performing a method of improving data throughput on a motherboard.
    • Mounting an integrated CPU and interface controller as a single chip on the motherboard.
    • Connecting an LVDS channel directly to the interface controller, the channel comprising two unidirectional, serial channels to transmit data in opposite directions.
    • Increasing data throughput by providing each channel with multiple differential signal line pairs.
    • Configuring the interface controller to adapt to different numbers of differential signal line pairs to convey encoded address and data bits of a PCI bus transaction in serial form.
    • Coupling the integrated CPU and interface device to a peripheral device through the channel.
  • The complaint reserves the right to assert additional claims (Compl. ¶¶136, 139, 142).

U.S. Patent No. 9,529,769 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction In Opposite Directions"

  • Patent Identification: U.S. Patent No. 9,529,769, "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction In Opposite Directions," issued December 27, 2016.
  • Technology Synopsis: This patent describes a computer system and method for improving peripheral communication. The invention involves obtaining an integrated CPU and graphics controller and using separate LVDS channels to convey both USB protocol data and digital video data through a connector to an external device (Compl. ¶¶149, 152).
  • Asserted Claims: At least independent claim 19 is asserted (Compl. ¶¶149, 152).
  • Accused Features: The complaint alleges infringement by tablets and laptops (e.g., iPad Pro, MacBook Pro) that use an integrated SoC (e.g., A9X, Intel Kaby Lake) to output both USB 3.x data and digital video data (e.g., DisplayPort) through a single physical connector like a Lightning port or USB-C port (Compl. ¶¶149, 152).

U.S. Patent No. RE45,140 - "Data Security Method and Device for Computer Modules"

  • Patent Identification: U.S. Patent No. RE45,140, "Data Security Method and Device for Computer Modules," issued September 16, 2014. This is a reissue of U.S. Patent No. 6,643,777.
  • Technology Synopsis: The patent claims a method of improving computer performance by integrating a CPU and graphics controller into a single chip. This integrated chip is then directly connected to LVDS channels to convey serialized PCI bus transactions and to separate differential signal channels to output digital video data (Compl. ¶161). It is also connected directly to memory (Compl. ¶161(f)).
  • Asserted Claims: At least independent claim 30 is asserted (Compl. ¶¶161, 164, 167).
  • Accused Features: The accused features include smartphones, tablets, and laptops that use an integrated SoC (e.g., A9, A9X, Intel Kaby Lake) which connects directly to PCIe channels, MIPI DSI or DisplayPort channels for video, and DDR memory (Compl. ¶¶161, 164, 167).

U.S. Patent No. RE44,654 - "Data Security Method and Device for Computer Modules"

  • Patent Identification: U.S. Patent No. RE44,654, "Data Security Method and Device for Computer Modules," issued December 17, 2013. This is also a reissue of U.S. Patent No. 6,643,777.
  • Technology Synopsis: This patent describes a method for increasing external data communication speed. The method involves providing an integrated CPU and graphics controller on a circuit board and connecting it to multiple LVDS channels, including a first channel for general data and a second channel for transmitting USB protocol data through a connector to a console (Compl. ¶¶176, 179).
  • Asserted Claims: At least independent claim 20 is asserted (Compl. ¶¶176, 179).
  • Accused Features: The accused features are tablets and laptops (e.g., iPad Pro, MacBook Pro) that use an integrated SoC and a connector (Lightning or USB-C) to connect to a console and transmit USB protocol data via LVDS channels (Compl. ¶¶176, 179).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies three categories of accused products manufactured by Defendant Hon Hai: "Accused Hon Hai Smartphones," "Accused Hon Hai Tablets," and "Accused Hon Hai Laptops" (Compl. ¶72). Exemplary products cited for illustrative purposes include the iPhone 6s, the iPad Pro (12.9"), and the MacBook Pro (13-inch, 2017) (Compl. ¶¶76, 90, 103).

Functionality and Market Context

  • The complaint alleges that these products are computer systems built around a System-on-Chip (SoC) or highly integrated processor, such as Apple's A9/A9X SoC or Intel's 7th Generation Core i5 ("Kaby Lake") processor (Compl. ¶¶78, 92, 105).
  • A block diagram of the iPhone 6s system architecture shows the central A9 SoC directly connected to various I/O interfaces, including PCIe and USB (Compl. p. 36). The core of the infringement allegations is that these SoCs integrate the CPU, graphics controller, and interface controllers onto a single chip (Compl. ¶¶80, 83, 93).
  • These SoCs are alleged to connect directly to various high-speed serial interfaces that the complaint characterizes as "LVDS channels." These include PCIe for connecting to flash storage, MIPI DSI for connecting to the internal display, and external-facing ports like Lightning or USB-C for conveying USB and/or DisplayPort data (Compl. ¶¶81, 82, 84, 86, 87, 108, 110, 111). A diagram from an Intel datasheet for the accused Kaby Lake processor shows the SoC with direct outputs for PCIe, USB 3.0, and DisplayPort (Compl. p. 54).
  • The complaint asserts that Hon Hai is the "world's largest contract electronics maker" and that its sales of the accused products generate billions of dollars in revenue (Compl. ¶¶7, 67).

IV. Analysis of Infringement Allegations

’750 Patent Infringement Allegations

Claim Element (from Independent Claim 50) Alleged Infringing Functionality Complaint Citation Patent Citation
a method of improving external peripheral data communication of a computer Defendant manufactures computer products (tablets, laptops) that improve peripheral data communication (Compl. ¶¶122(a), 125(a)). ¶122, ¶125 col. 2:42-49
obtaining an integrated obtains an integrated CPU and graphics controller as a single chip The exemplary tablet uses an Apple A9X SoC, and the exemplary laptop uses a 7th Gen Intel Core i5 processor, both of which are single chips containing an integrated CPU and graphics controller (Compl. ¶¶92, 93, 107). ¶122(b), ¶125(b) col. 4:26-30
connecting a first unidirectional, differential signal pair channel directly to the integrated CPU and graphics controller to output digital video data The A9X SoC in the tablet connects to MIPI DSI or LPDP channels; the Intel processor in the laptop connects to DDI and eDP channels. These are alleged to be unidirectional, differential signal channels outputting video data (Compl. ¶¶122(c), 125(c)). ¶122(c), ¶125(c) col. 6:20-27
providing a connector for external peripheral data communication The exemplary tablet has a Lightning port; the exemplary laptop has USB-C ports (Compl. ¶¶122(d), 125(d)). ¶122(d), ¶125(d) col. 3:45-51
providing an LVDS channel to convey USB protocol data through a connector that uses two unidirectional, serial bit channels that transmit data in opposite directions The Lightning port on the tablet and the USB-C ports on the laptop are alleged to be LVDS channels that convey USB 3.x data using two unidirectional channels for opposite-direction data transmission (Compl. ¶¶122(e), 125(e)). ¶122(e), ¶125(e) col. 5:5-13

’797 Patent Infringement Allegations

Claim Element (from Independent Claim 36) Alleged Infringing Functionality Complaint Citation Patent Citation
a method of improving data throughput on a motherboard Defendant manufactures smartphones, tablets, and laptops containing motherboards where data throughput is improved by the claimed method (Compl. ¶¶134(a), 137(a), 140(a)). ¶134, ¶137, ¶140 col. 34:1-4
mounting an integrated CPU and interface controller as a single chip on the motherboard The accused products use SoCs (A9, A9X, Intel Kaby Lake) that integrate the CPU and interface controllers (e.g., for PCIe) on a single chip mounted to the motherboard (Compl. ¶¶83, 134(b), 137(b), 140(b)). ¶83, ¶134(b) col. 35:20-24
connecting an LVDS channel directly to the interface controller, which LVDS channel comprises two unidirectional, serial channels to transmit data in opposite directions The SoCs in the accused products directly connect to PCIe channels, which are alleged to be LVDS channels with two unidirectional serial paths (Tx/Rx) (Compl. ¶¶82, 134(c), 137(c), 140(c)). ¶82, ¶134(c) col. 36:25-34
increasing data throughput in the serial channels by providing each channel with multiple differential signal line pairs The PCIe channels in the accused products have pairs of differential signal lanes, which increases data throughput (Compl. ¶¶134(d), 137(d), 140(d)). ¶134(d), ¶137(d) col. 35:36-40
configuring the interface controller to adapt to different numbers of differential signal line pairs to convey encoded address and data bits of a PCI bus transaction in serial form The integrated interface controllers in the SoCs are configured to convey PCIe data signals (which allegedly correspond to PCI transaction bits) through PCIe channels having differential signal line pairs (Compl. ¶¶134(e), 137(e), 140(e)). ¶134(e), ¶137(e) col. 35:41-47
coupling the integrated CPU and interface device to a peripheral device such as flash storage, which is attached to the motherboard through a PCIe channel The SoCs in the accused products are coupled to flash storage via a PCIe channel on the motherboard (Compl. ¶¶82, 134(f), 137(f), 140(f)). ¶82, ¶134(f) col. 36:48-52

Identified Points of Contention

  • Scope Questions: A central issue may be whether the term "Peripheral Component Interconnect (PCI) bus transaction," as used in patents with a 1999 priority date, can be construed to read on the modern, packet-based serial PCI Express (PCIe) protocol used in the accused products. The complaint argues that PCIe maintains the same "usage model and load-store communication model" as PCI, making it a backward-compatible evolution (Compl. ¶57). Another question is whether standardized interfaces like PCIe, USB 3.x, and MIPI DSI fall within the scope of the term "Low Voltage Differential Signal (LVDS) channel" as used in the patents.
  • Technical Questions: The infringement theories rely on the allegation that the SoCs in the accused products contain an "interface controller" that performs the functions required by the claims, such as adapting to different numbers of signal lines. The case may raise the question of what evidence demonstrates that the integrated logic blocks within the Apple A9/A9X and Intel SoCs perform the specific configuration and adaptation steps recited in claim 36 of the ’797 Patent.

V. Key Claim Terms for Construction

  • The Term: "Peripheral Component Interconnect (PCI) bus transaction"

    • Context and Importance: This term's construction is critical because the patents claim priority to 1999, when the parallel PCI standard was dominant, while the accused products utilize the serial PCIe standard. The outcome of the case may depend on whether the older term can encompass the newer technology.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The complaint alleges that PCIe "employs the same usage model and load-store communication model as PCI" and supports the same fundamental transactions, such as memory read/write (Compl. ¶57). If the patent specification describes the "transaction" at this functional level, it may support a broader construction.
      • Evidence for a Narrower Interpretation: The patent specification may describe the "transaction" by referencing specific signals and timings of the parallel PCI 2.x standard (e.g., FRAME#, IRDY#, DEVSEL#). Such specific disclosures could be used to argue that a "PCI bus transaction" is limited to the parallel protocol and does not read on the packet-based serial protocol of PCIe, which lacks these signals.

  • The Term: "Low Voltage Differential Signal (LVDS) channel"

    • Context and Importance: The infringement allegations identify numerous modern, standardized interfaces—including PCIe, USB 3.x, MIPI DSI, and DisplayPort—as infringing "LVDS channels" (Compl. ¶¶55, 63, 84). The definition of this term will determine whether these distinct protocols are within the claims' scope.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent may define the term functionally as any communication path that uses low-voltage differential signaling for its physical layer, which would likely encompass the accused interfaces as alleged by the Plaintiff (Compl. ¶1).
      • Evidence for a Narrower Interpretation: The specification's embodiments might disclose a specific, non-standardized point-to-point LVDS implementation. A defendant could argue that the term should be limited to that disclosure and does not cover the more complex, standardized protocols of PCIe or USB, which include additional layers of logic, packet structures, and control features not described in the patent.

VI. Other Allegations

The complaint bases its infringement counts on direct infringement under 35 U.S.C. § 271(g), which concerns the importation, sale, or use of a product made by a process patented in the United States (Compl. ¶¶120, 132, 147, 159, 174). The complaint does not contain explicit counts or factual allegations supporting indirect or willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of temporal and definitional scope: Can the term "PCI bus transaction," rooted in the technical context of the 1999 parallel bus standard, be construed to cover the serialized, packet-based data transmissions of the modern PCIe protocol? The answer will likely define the reach of the patent portfolio over modern electronics.
  • A key evidentiary question will be one of process infringement: To succeed under § 271(g), the Plaintiff must prove not only that the final product has certain features, but that the Defendant's overseas manufacturing process practiced the steps of the asserted method claims. This will require evidence showing, for example, that the act of mounting an integrated SoC on a motherboard and connecting its pins constitutes "connecting an LVDS channel directly to the interface controller" as claimed.
  • A final question will be one of technological classification: Does the term "LVDS channel" refer broadly to the underlying electrical signaling standard, thereby encompassing a wide range of modern I/O protocols like PCIe and USB 3.x as alleged, or does the patent's context limit it to a more specific implementation, potentially placing the accused standardized interfaces outside the claims?