DCT

6:23-cv-00265

Acqis LLC v. Quanta Computer Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:23-cv-00265, W.D. Tex., 09/05/2024
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign corporation not resident in the United States and may be sued in any judicial district. The complaint also notes that the asserted patents have been previously litigated in this District.
  • Core Dispute: Plaintiff alleges that Defendant’s laptops, desktops, and servers infringe ten patents related to high-speed, low-power serial data transmission technologies for computer interconnections.
  • Technical Context: The technology concerns methods of replacing parallel data buses with serial, low-voltage differential signaling (LVDS) channels to increase data speed and efficiency, a foundational concept for modern standards like PCI Express (PCIe) and USB 3.x.
  • Key Procedural History: The complaint alleges that Plaintiff provided Defendant with actual notice of infringement of the asserted patents on or around May 14, 2018. It also references a prior lawsuit involving related ACQIS patents that resulted in a jury verdict against IBM, a fact which may be relevant to allegations of willful infringement.

Case Timeline

Date Event
1999-05-14 Earliest Priority Date ('768, '750, '359, '977, '797, '436, '140, '654 Patents)
2005-02-10 Priority Date ('739 Patent)
2005-03-31 Priority Date ('769 Patent)
2012-07-31 Issue Date (U.S. Patent No. 8,234,436)
2013-12-17 Issue Date (U.S. Patent No. RE44,654)
2014-01-07 Issue Date (U.S. Patent No. 8,626,977)
2014-01-28 Issue Date (U.S. Patent No. RE44,739)
2014-06-17 Issue Date (U.S. Patent No. 8,756,359)
2014-09-16 Issue Date (U.S. Patent No. RE45,140)
2015-03-10 Issue Date (U.S. Patent No. 8,977,797)
2016-12-27 Issue Date (U.S. Patent No. 9,529,768)
2016-12-27 Issue Date (U.S. Patent No. 9,529,769)
2017-01-01 Approximate Launch Date (Exemplary Accused Products: 2017 MacBook Pro, iMac)
2017-07-11 Issue Date (U.S. Patent No. 9,703,750)
2018-05-14 Plaintiff alleges providing actual notice of infringement to Defendant
2024-09-05 First Amended Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,529,768 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions"

  • Patent Identification: U.S. Patent No. US9529768B2, "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions," issued December 27, 2016.
  • The Invention Explained:
    • Problem Addressed: The complaint describes that traditional computer interconnections, such as for the Peripheral Component Interconnect (PCI) bus, used parallel data transmission requiring a large number of signal channels and connector pins, which made them power-inefficient, noisy, and ill-suited for "cable friendly" Low Voltage Differential Signal (LVDS) channels (Compl. ¶44).
    • The Patented Solution: The invention proposes a computer system architecture where a central processing unit (CPU) and an interface controller are integrated into a single chip (Compl. ¶143; '436 Patent, col. 29:20-22). This integrated unit connects directly to an LVDS channel that uses pairs of unidirectional, differential signal paths to serially transmit data from PCI bus transactions in opposite directions, thereby reducing pin count and power consumption (Compl. ¶44, 58).
    • Technical Importance: This approach of serializing parallel bus data over differential signal pairs is a foundational principle of modern high-speed interconnects like PCI Express, which enabled significant improvements in computer performance and scalability (Compl. ¶59-62).
  • Key Claims at a Glance:
    • The complaint asserts at least independent claim 13 (Compl. ¶143, 146, 149).
    • Claim 13 requires:
      • An integrated central processing unit (CPU) and interface controller in a single chip;
      • A first low voltage differential signal (LVDS) channel directly extending from the interface controller to convey address and data bits of a PCI bus transaction in a serial bit stream;
      • Wherein the LVDS channel comprises first and second unidirectional, multiple, differential signal pairs to convey data in opposite directions through different numbers of differential signal pairs; and
      • System memory directly coupled to the integrated CPU and interface controller.
    • The complaint notes that additional infringed claims will be identified during discovery (Compl. ¶145).

U.S. Patent No. 9,703,750 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions"

  • Patent Identification: U.S. Patent No. US9703750B2, "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions," issued July 11, 2017.
  • The Invention Explained:
    • Problem Addressed: As with the '768 patent, this invention addresses the inefficiency of high pin-count, parallel bus architectures for interconnecting computer components (Compl. ¶44).
    • The Patented Solution: The patent describes a computer system with a CPU and interface controller integrated on a single chip, directly connected to an LVDS channel for bidirectional data transfer (Compl. ¶160; '436 Patent, Abstract). This channel serially conveys all components of a PCI bus transaction—address bits, data bits, and byte enable information bits—using a pair of unidirectional, differential signal paths ('750 Patent, Claim 1). This architecture aims to be scalable and reduce the pin-count required for connectors (Compl. ¶62).
    • Technical Importance: This technology relates to the fundamental architecture of the PCI Express standard, which replaced the parallel PCI bus and is now a ubiquitous high-speed interface in modern computers (Compl. ¶59, 61).
  • Key Claims at a Glance:
    • The complaint asserts at least independent claim 1 (Compl. ¶160, 163, 166).
    • Claim 1 requires:
      • An integrated central processing unit (CPU) and interface controller in a single chip;
      • A first low voltage differential signal (LVDS) channel directly extending from the interface controller to convey address bits, data bits, and byte enable information bits of a PCI bus transaction in a serial bit stream;
      • Wherein the first LVDS channel comprises a first unidirectional, differential signal pair for data in a first direction and a second unidirectional, differential signal pair for data in a second, opposite direction; and
      • System memory directly coupled to the integrated CPU and interface controller.
    • The complaint states that its allegations are not limited to claim 1 and that additional claims will be identified (Compl. ¶162).

Multi-Patent Capsules

  • U.S. Patent No. 8,756,359: "Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits," issued June 17, 2014. This patent describes a computer system having a CPU and a variety of connectors, with LVDS channels extending from the CPU to convey PCI or USB data packets. Independent claim 6 is asserted. The accused features include the CPU's direct connection to PCIe and USB 3.x channels and the provision of USB-C ports for console connectivity (Compl. ¶177, 180, 183).

  • U.S. Patent No. 8,626,977: "Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits," issued January 7, 2014. This patent covers a computer with an integrated CPU and graphics subsystem in a single chip, using an LVDS channel for PCI bus transactions and other serial channels for USB protocol data. Independent claim 1 is asserted. The accused features are the integrated Intel processors that output digital video and have direct connections to PCIe and USB-C 3.x ports (Compl. ¶194, 197).

  • U.S. Patent No. RE44,739: "Data Security Method and Device for Computer Modules," issued January 28, 2014. This patent relates to a computer system with an integrated CPU and graphics controller coupled to a first channel for conveying video information and a second LVDS channel with bidirectional lanes for transmitting data such as USB protocol data. Independent claim 18 is asserted. The accused features are the integrated Intel processors that connect to channels for digital video (eDP/DDI) and to LVDS channels for USB 3.x data via USB-C ports (Compl. ¶208, 211).

  • U.S. Patent No. 8,977,797: "Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel," issued March 10, 2015. This patent claims a method of manufacturing that involves mounting an integrated CPU/interface controller on a motherboard and connecting an LVDS channel directly to it to improve data throughput. Independent claim 36 is asserted. The accused features are Defendant’s alleged manufacturing processes for its laptops and desktops that incorporate Intel processors with integrated PCIe/OPI interfaces (Compl. ¶223, 226).

  • U.S. Patent No. 9,529,769: "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction In Opposite Directions," issued December 27, 2016. This patent claims a method of improving peripheral data communication by obtaining an integrated CPU/graphics controller and connecting it to unidirectional channels for video and LVDS channels for USB protocol data. Independent claim 19 is asserted. The accused features are Defendant’s alleged manufacturing processes for its laptops and desktops that provide connectors for USB 3.x data and DisplayPort/Thunderbolt video signals (Compl. ¶240, 243).

  • U.S. Patent No. RE45,140: "Data Security Method and Device for Computer Modules," issued September 16, 2014. This patent describes a method of improving computer performance by obtaining an integrated CPU/graphics controller and connecting it to various LVDS and differential signal channels for bidirectional data and video output. Independent claim 35 is asserted. The accused features are the alleged manufacturing processes for the accused laptops and desktops which connect integrated processors to PCIe/OPI channels and provide USB-C connectors for USB 3.x and Thunderbolt (Compl. ¶255, 258).

  • U.S. Patent No. RE44,654: "Data Security Method and Device for Computer Modules," issued December 17, 2013. This patent claims a method of increasing data communication speed by connecting a CPU directly to a peripheral bridge on a circuit board and connecting LVDS channels for data transfer to the bridge and to external connectors. Independent claim 23 is asserted. The accused features are the alleged manufacturing processes wherein a CPU is connected to a Platform Controller Hub (PCH) via an OPI/DMI link, with PCIe and USB-C channels connected to the PCH (Compl. ¶270, 273, 276).

  • U.S. Patent No. 8,234,436: "Computer System Including Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits," issued July 31, 2012. This patent describes a computer with an integrated CPU and peripheral controller coupled to multiple LVDS channels for PCI transactions and a second LVDS channel for digital video data. Independent claim 13 is asserted. The accused features include the use of Intel processors with direct connections to PCIe/OPI channels for data and eDP/DDI channels for video (Compl. ¶287, 290).

III. The Accused Instrumentality

  • Product Identification: The complaint identifies three categories of accused products: "Accused Quanta Laptops" (e.g., MacBook, MacBook Air, MacBook Pro), "Accused Quanta Desktops" (e.g., iMac, iMac Pro, Mac Mini), and "Accused Quanta Servers" (e.g., QuantaGrid, QuantaPlex, STRATOS) (Compl. ¶75-78).
  • Functionality and Market Context: The complaint alleges these products are computer systems that incorporate processors, such as Intel's 7th Generation "Kaby Lake" Core processors or Intel Xeon processors, which integrate a CPU and interface controllers for high-speed serial data links onto a single chip (Compl. ¶88, 103, 116). These processors are allegedly connected directly to LVDS channels, such as PCIe, USB 3.x, and On-Package Interface (OPI) or Direct Media Interface (DMI) links, which convey data in serial bit streams using unidirectional pairs of lanes (Compl. ¶90, 105, 118). An Intel processor diagram from a technical datasheet is provided to illustrate these direct connections from the processor to various interfaces, including PCIe and USB 3.x (Compl. ¶88, p. 27). The complaint asserts that Quanta is a "global leader" in the computer market and that exports to the U.S. constitute a major portion of its business (Compl. ¶70, 73).

IV. Analysis of Infringement Allegations

'768 Patent Infringement Allegations

Claim Element (from Independent Claim 13) Alleged Infringing Functionality Complaint Citation Patent Citation
a computer, comprising: an integrated central processing unit (CPU) and interface controller in a single chip; The exemplary MacBook Pro laptop contains a 7th Generation Intel® Core™ i5 (“Kaby Lake”) Processor, which integrates the CPU and interface controllers for driving interfaces like PCIe channels on a single chip. ¶88, 143(b) '436 Patent, col. 29:20-22
a first low voltage differential signal (LVDS) channel directly extending from the interface controller to convey address and data bits of a PCI bus transaction in a serial bit stream, The Kaby Lake processor includes PCIe channels that directly extend from the integrated interface controller. The complaint alleges PCIe channels are LVDS channels that convey data bits of a PCI bus transaction serially. ¶90, 143(c) '436 Patent, col. 3:65-4:2
wherein the first LVDS channel comprises first unidirectional, multiple, differential signal pairs to convey data in a first direction and second unidirectional, multiple, differential signal pairs to convey data in a second, opposite direction through different numbers of differential signal pairs; and The PCIe standard defines configurations with different numbers of serial lane pairs (e.g., x1, x2, x4) for data transmission in opposite directions. ¶62, 143(c) '436 Patent, col. 37:37-43
system memory directly coupled to the integrated CPU and interface controller. The exemplary laptop’s processor is directly coupled to its DDR3 system memory. ¶93, 143(d) '436 Patent, col. 29:32-34

'750 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a computer, comprising: an integrated central processing unit (CPU) and interface controller in a single chip; The exemplary MacBook Pro laptop contains a 7th Generation Intel® Core™ i5 (“Kaby Lake”) Processor, which integrates the CPU and interface controllers for driving interfaces like PCIe channels on a single chip. ¶88, 160(b) '436 Patent, col. 29:20-22
a first low voltage differential signal (LVDS) channel directly extending from the interface controller to convey address bits, data bits, and byte enable information bits of a PCI bus transaction in a serial bit stream, The Kaby Lake processor includes numerous PCIe channels that directly extend from the integrated interface controller. The complaint alleges these channels convey address, data, and byte enable bits of a PCI bus transaction serially. ¶60, 90, 160(c) '436 Patent, col. 3:65-4:2
wherein the first LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; and PCIe channels are alleged to use pairs of unidirectional, differential signal lanes to convey information in opposite directions. ¶62, 160(c) '436 Patent, col. 37:37-43
system memory directly coupled to the integrated CPU and interface controller. The exemplary laptop’s processor is directly coupled to its DDR3 system memory. ¶93, 160(d) '436 Patent, col. 29:32-34
  • Identified Points of Contention:
    • Scope Questions: A central issue may be whether the term "PCI bus transaction," as used in patents with a 1999 priority date, can be construed to read on data packets transmitted over a modern PCI Express bus. The complaint alleges backward software compatibility between PCIe and PCI to support this theory (Compl. ¶61), but the underlying hardware protocols are different. Another question is whether the claim term "low voltage differential signal (LVDS) channel" is a generic term encompassing standardized interfaces like PCIe and USB 3.x, or if it is limited by the specification to a more specific, proprietary bus architecture.
    • Technical Questions: For the '768 patent, a key technical question will be whether the different lane configurations of PCIe (e.g., x1, x4, x8) satisfy the claim limitation "through different numbers of differential signal pairs" in the manner required by the claim. For the '750 patent, a question is what evidence the complaint provides that the accused PCIe channels convey "byte enable information bits" of a PCI bus transaction, a specific technical detail of the original PCI standard (Compl. ¶60). The complaint presents a diagram of a PCI Express Transaction Layer Packet showing a "BE" field to support this allegation (Compl. ¶60, p. 17).

V. Key Claim Terms for Construction

  • The Term: "low voltage differential signal (LVDS) channel"

  • Context and Importance: The applicability of the patents to the accused products, which use modern standardized interfaces like PCIe and USB 3.x, hinges on whether these interfaces fall within the definition of an "LVDS channel." Practitioners may focus on this term because the plaintiff's infringement theory requires a broad, functional definition rather than one tied to a specific, non-standardized implementation.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification of the related '436 Patent states that "the term LVDS is herein used to generically refer to low voltage differential signals and is not intended to be limited to any particular type of LVDS technology" ('436 Patent, col. 4:1-4). This may support a construction covering any channel using the underlying signaling method.
    • Evidence for a Narrower Interpretation: The patents' detailed descriptions heavily feature a proprietary architecture termed "XPBus" ('436 Patent, Fig. 6, 618). A defendant may argue that the term "LVDS channel" should be construed in light of these specific embodiments and limited to proprietary, non-standardized interconnects rather than industry-wide standards like PCIe.

  • The Term: "interface controller"

  • Context and Importance: This term is central because the claims require it to be integrated with the CPU "in a single chip." The infringement allegation depends on mapping this term to the PCIe root complex and other I/O logic integrated into modern Intel processors.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The claims describe the "interface controller" functionally as the component from which the LVDS channel "directly extend[s]" and which conveys PCI bus transactions. This functional language may support reading the term on any integrated processor logic that performs this role. The complaint provides a processor line platform diagram to illustrate this integrated functionality (Compl. ¶88, p. 27).
    • Evidence for a Narrower Interpretation: The detailed description of the related '436 patent discloses a specific "Host Interface Controller (HIC)" and "Peripheral Interface Controller (PIC)" that perform translation between a parallel PCI bus and the serial XPBus ('436 Patent, Fig. 9). A defendant may argue that the claimed "interface controller" should be limited to a component that performs this specific translation function, which is technically distinct from a native PCIe controller.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement under 35 U.S.C. § 271(b). It asserts that Quanta, with knowledge of the ACQIS patents since at least May 2018, took affirmative steps to induce infringement by its customers (importers, resellers, end users) by selling and importing the Accused Quanta Products into the United States with the specific intent that they be used in an infringing manner (Compl. ¶135-138).
  • Willful Infringement: The complaint alleges willful infringement based on Quanta's alleged continuation of infringing activities after receiving actual notice of the ACQIS Patents on or around May 14, 2018 (Compl. ¶129, 131, 134).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can the term "LVDS channel," rooted in the patent's disclosure of a proprietary serial bus, be construed broadly enough to encompass standardized, next-generation serial interconnects like PCI Express, which post-date the patent's priority but are alleged to embody its core principles?
  • A second central question will be one of technological translation: does the data packet structure of the accused PCI Express standard meet the specific claim requirement of conveying the "address and data bits of a PCI bus transaction," or has the technology evolved such that there is a fundamental mismatch between the claimed legacy protocol and the accused modern protocol?
  • A key evidentiary question will concern willfulness: given the allegation of actual notice in 2018, the case may turn on what steps, if any, Quanta took to assess the infringement allegations, which will be central to determining whether any continued infringement was willful.