Teleputers LLC v. Qualcomm Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Teleputers, LLC (New Jersey)
  • Defendant: QUALCOMM Incorporated, and QUALCOMM Technologies, Inc. (Delaware)
  • Plaintiff’s Counsel: The Mort Law Firm, PLLC
• Case Identification: 6:23-cv-00404, W.D. Tex., 05/26/2023
• Venue Allegations: Plaintiff alleges venue is proper because Defendant has a regular and established place of business in the district and has committed acts of infringement there.
• Core Dispute: Plaintiff alleges that Defendant’s Systems-on-Chips (SoCs) containing ARM NEON technology infringe patents related to methods for efficiently performing data permutations in a programmable processor.
• Technical Context: The technology concerns methods for rearranging sequences of bits or subwords (e.g., pixels) within a processor, a fundamental operation for performance-intensive applications like cryptography and 2-D multimedia processing.
• Key Procedural History: The complaint identifies four other lawsuits filed by Teleputers against different semiconductor companies (Renesas, Marvell, Oracle, Fujitsu), suggesting a broader, ongoing assertion campaign involving this patent portfolio.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,952,478 - Method and system for performing permutations using permutation instructions based on modified omega and flip stages

• Issued: October 4, 2005

The Invention Explained

• Problem Addressed: The patent describes that performing arbitrary bit-level permutations (rearranging individual bits) is computationally difficult and slow on conventional processors, which are word-oriented. This creates a bottleneck for applications like cryptography that rely heavily on such operations (’478 Patent, col. 1:40-51).
• The Patented Solution: The invention proposes a method to perform any arbitrary permutation through a sequence of simpler, predefined permutation instructions. These instructions are based on the stages of a theoretical "omega-flip" network. Instead of building the entire complex network in hardware, the method achieves the same result by iteratively applying a series of simpler instructions, where the output of one step becomes the input for the next, until the final desired bit order is achieved (’478 Patent, Abstract; col. 4:50-64).
• Technical Importance: This approach offered a more efficient software-based method for complex bit-shuffling operations than prior art methods that were either too slow or required impractically large memory look-up tables (’478 Patent, col. 2:6-28).

Key Claims at a Glance

• The complaint asserts independent claim 1 (Compl. ¶20).
• Essential elements of claim 1:
  • A method of performing an arbitrary permutation of a source sequence of bits in a programmable processor comprising the steps of:
  • a. defining an intermediate sequence of bits that said source sequence of bits is transformed into;
  • b. determining a permutation instruction for transforming said source sequence of bits into said intermediate sequence of bits; and
  • c. repeating steps a. and b. using said determined intermediate sequence of bits from step b. as said source sequence of bits in step a. until a desired sequence of bits is obtained,
  • wherein the determined permutation instructions form a permutation instruction sequence.

U.S. Patent No. 7,092,526 - Method and system for performing subword permutation instructions for use in two-dimensional multimedia processing

• Issued: August 15, 2006

The Invention Explained

• Problem Addressed: The patent addresses the challenge of efficiently processing two-dimensional (2-D) data, such as images and video, on processors designed for one-dimensional, linear data streams. A key difficulty is permuting subwords (e.g., pixels) across multiple registers to enable parallel processing (’526 Patent, col. 1:14-24).
• The Patented Solution: The invention provides a set of permutation instructions for 2-D data by first "decomposing" the data into a fundamental "atomic element," defined as a 2x2 matrix. The patent then describes permutation instructions that rearrange the data elements (subwords) within this 2x2 atomic unit (e.g., transposing, rotating). By performing these atomic-level permutations, larger and more complex 2-D data manipulations can be built up hierarchically (’526 Patent, Abstract; col. 3:1-10).
• Technical Importance: This methodology provides a structured way to perform common 2-D data manipulations directly on packed subword data, which is more efficient for graphics and video processing than using general-purpose instructions (’526 Patent, col. 4:40-47).

Key Claims at a Glance

• The complaint asserts independent claim 1 (Compl. ¶26).
• Essential elements of claim 1:
  • A method for permuting two dimensional (2-D) data in a programmable processor comprising the steps of:
  • decomposing said two dimensional data into at least one atomic element... said at least one atomic element of said two dimensional data is a 2x2 matrix...;
  • determining at least one permutation instruction for rearrangement of said data in said atomic element;
  • said data elements being rearranged by said at least one permutation instruction, each of said data elements representing a subword having one or more bits; and
  • applying said permutation instructions to said subwords and placing said permutated subwords into a destination register.

III. The Accused Instrumentality

Product Identification

• The complaint identifies the Qualcomm CSRS3703 System-on-Chip (SoC) as an exemplary accused instrumentality (Compl. ¶18).

Functionality and Market Context

• The accused CSRS3703 is an application processor designed for automotive infotainment systems (Compl. p. 7). Its core functionality relevant to the suit is the inclusion of a dual-core ARM Cortex-A7 CPU, which implements the ARM NEON advanced SIMD (Single Instruction, Multiple Data) architecture (Compl. p. 7-8). The complaint alleges that permutation instructions within the NEON instruction set, such as VTRN (Vector Transpose), are used to perform the patented methods (Compl. p. 10).
• The complaint provides a block diagram of the CSRatlas7 SoC, illustrating its integration of the Cortex-A7 with NEON technology alongside other components for infotainment applications (Compl. p. 8).

IV. Analysis of Infringement Allegations

’478 Patent Infringement Allegations

The complaint alleges that performing complex permutations by applying a series of NEON instructions meets the elements of claim 1. A diagram from an ARM blog post is used as evidence, showing a "Source sequence," an "Intermediate sequence," and a "Permutation Instruction," which correspond to the claim's terminology (Compl. p. 11).

Identified Points of Contention

• Scope Questions: A central issue may be the meaning of "determining a permutation instruction." The question is whether this claim element is met by simply selecting a pre-existing instruction (like VTRN) from a processor's instruction set, or if it requires performing the specific algorithm described in the patent for deriving instructions from a theoretical Benes network (’478 Patent, FIG. 5A).
• Technical Questions: The complaint alleges that using the NEON instructions constitutes infringement. It does not provide evidence that Qualcomm performs the patent's specific method for deriving or generating those instructions. The case may turn on whether claim 1 covers the mere execution of a sequence of permutation instructions or if it is limited to the patent's specific method for creating that sequence.

’526 Patent Infringement Allegations

The complaint alleges that the NEON VTRN instruction infringes by operating on data as if it were a 2x2 matrix. A provided screenshot from ARM documentation states that VTRN "treats the elements of its operand vectors as elements of 2 x 2 matrices, and transposes the matrices," which the complaint maps to the claim's "atomic element" language (Compl. p. 18).

Identified Points of Contention

• Scope Questions: The dispute will likely focus on whether the VTRN instruction’s function constitutes "decomposing" data into a 2x2 "atomic element." A question for the court is whether an instruction that inherently operates on data as if it were in a 2x2 matrix performs the explicit "decomposing" step required by the claim.
• Technical Questions: Claim 1 recites a sequence where "decomposing" is the first step, followed by "determining" an instruction. A key question is whether the accused functionality follows this sequence. It may be argued that the 2x2 matrix behavior is not a preparatory decomposition step but is rather the inseparable, inherent function of the VTRN instruction itself.

V. Key Claim Terms for Construction

Term: "determining a permutation instruction" (’478 Patent, Claim 1)

• Context and Importance: This term is critical to the scope of the ’478 patent. Its construction will likely decide whether the act of selecting and using a processor's built-in permutation instructions falls within the claim, or if the claim is limited to the patent's specific method for generating such instructions. Practitioners may focus on this term because the infringement theory rests on equating the selection of a VTRN instruction with the patent's "determining" step.
• Intrinsic Evidence for a Broader Interpretation: The patent states its goal is performing permutations "in a programmable processor" (’478 Patent, col. 1:14-16), which could suggest that using the available instructions of such a processor is the intended context.
• Intrinsic Evidence for a Narrower Interpretation: The specification details a specific multi-step method for "implementing OMFLIP instructions," which involves translating the configuration of a Benes network (’478 Patent, FIG. 5A, col. 9:5-11). This suggests "determining" may refer to this specific, inventive algorithmic process, not a generic selection.

Term: "decomposing said two dimensional data into at least one atomic element" (’526 Patent, Claim 1)

• Context and Importance: This is the first recited step of the method in claim 1 of the ’526 patent. Infringement depends on whether the accused product performs this action. The dispute may center on whether "decomposing" is an active data preparation step or a conceptual description of an instruction's function.
• Intrinsic Evidence for a Broader Interpretation: The patent’s abstract states it provides primitives "based on decomposing images and objects into atomic units." This focus on the "basis" could support an interpretation where any instruction that achieves the result of an atomic-unit permutation is covered.
• Intrinsic Evidence for a Narrower Interpretation: The patent’s flow diagram (FIG. 2) shows "Decomposing...into an atomic element" (12) as a distinct step that occurs before "Determining permutation instruction" (14). This ordering suggests "decomposing" is a prerequisite action, not an inherent property of the later-determined instruction.

VI. Other Allegations

Indirect Infringement

• The complaint alleges inducement of infringement for both patents. The factual basis provided is that Defendant encourages customers to use the accused products and provides technical support for their use (Compl. ¶22-23, ¶28-29). The complaint does not cite specific user manuals, data sheets, or other documents that allegedly instruct infringing use.

Willful Infringement

• The complaint alleges that Defendant has notice of the patents "at least by the date of this Original Complaint" (Compl. ¶15). This allegation appears to support a claim for post-filing willfulness only, as no facts supporting pre-suit knowledge are provided. The prayer for relief requests a finding that the case is exceptional under 35 U.S.C. § 285 (Compl. p. 21).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of infringement theory versus claim scope: For the ’478 patent, does "determining a permutation instruction" require performing the patent's specific algorithm for generating instructions from a theoretical network, or can it be read to cover the mere selection and sequential execution of pre-existing hardware instructions like ARM's VTRN?
• A second key issue will be the sequence of claimed steps: For the ’526 patent, does the accused functionality perform an explicit, antecedent step of "decomposing" 2-D data into 2x2 "atomic elements," or is the 2x2 matrix operation an inherent, inseparable function of the VTRN instruction itself, potentially creating a mismatch with the claim's required order of operations?
• An evidentiary question will be one of intent and instruction: For the indirect infringement claims, what specific evidence will Plaintiff present to show that Qualcomm's technical support, documentation, or developer tools actively instructed or encouraged customers to implement the multi-step permutation sequences or 2-D decomposition methods in a manner that directly infringes the patent claims?