DCT

6:23-cv-00465

InnoMemory LLC v. Rubrik Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:23-cv-00465, W.D. Tex., 06/26/2023
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant maintains a regular and established place of business within the Western District of Texas and has committed acts of infringement in the district.
  • Core Dispute: Plaintiff alleges that Defendant’s use of computing devices incorporating industry-standard DDR memory infringes two patents related to the architecture and power management of random-access memory circuits.
  • Technical Context: The technology at issue concerns the fundamental design of Dynamic Random-Access Memory (DRAM), focusing on methods to enhance performance and reduce power consumption during data read and refresh operations.
  • Key Procedural History: The complaint is a First Amended Complaint but does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history relevant to the patents-in-suit.

Case Timeline

Date Event
1999-02-13 U.S. Patent No. 6,240,046 Priority Date
2000-03-03 U.S. Patent No. 7,057,960 Priority Date
2001-05-29 U.S. Patent No. 6,240,046 Issues
2006-06-06 U.S. Patent No. 7,057,960 Issues
2023-06-26 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF READING EITHER ONE OR MORE THAN ONE DATA WORD IN A SINGLE CLOCK CYCLE"

  • Patent Identification: U.S. Patent No. 6,240,046, "INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF READING EITHER ONE OR MORE THAN ONE DATA WORD IN A SINGLE CLOCK CYCLE," issued May 29, 2001 (Compl. ¶6).

The Invention Explained

  • Problem Addressed: The patent describes a power-consumption dilemma in prior art memory devices. Systems that retrieve only one data word at a time are inefficient for sequential (burst) reads, while systems that always retrieve multiple data words waste power during random (single-word) reads, a particular concern for portable computing systems (’046 Patent, col. 2:3-15).
  • The Patented Solution: The invention discloses a memory circuit that can adapt its retrieval mode. It can retrieve a single data word in a single clock cycle to conserve power during random reads. Alternatively, for burst reads (identified by a "load read" request followed by an "advance" request), it can retrieve more than one data word from the memory array in one clock cycle, saving one word internally for subsequent output. This dual-mode capability is controlled by a flip-flop that tracks the access pattern (’046 Patent, Abstract; col. 2:45-56).
  • Technical Importance: This adaptive approach allows memory architecture to optimize for both power and performance depending on whether data access is random or sequential, a key trade-off in memory design (’046 Patent, col. 3:1-9).

Key Claims at a Glance

  • The complaint asserts independent claims 1, 9, and 15 (Compl. ¶12).
  • The essential elements of independent claim 1 include:
    • A random access memory integrated circuit comprising a memory array and a data bus wider than one data word.
    • The circuit is capable of retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle immediately following the first.
  • The complaint reserves the right to assert dependent claims from the asserted range of claims 1-19 (Compl. ¶12).

U.S. Patent No. 7,057,960 - "METHOD AND ARCHITECTURE FOR REDUCING THE POWER CONSUMPTION FOR MEMORY DEVICES IN REFRESH OPERATIONS"

  • Patent Identification: U.S. Patent No. 7,057,960, "METHOD AND ARCHITECTURE FOR REDUCING THE POWER CONSUMPTION FOR MEMORY DEVICES IN REFRESH OPERATIONS," issued June 6, 2006 (Compl. ¶14).

The Invention Explained

  • Problem Addressed: The patent states that conventional DRAMs consume significant power in standby mode because they refresh all memory cells, even if only a portion of the stored data needs to be retained. Furthermore, conventional refresh operations activate the periphery array circuits for all quadrants of the memory, which is inefficient when only a partial refresh is required (’960 Patent, col. 1:35-49; col. 2:25-29).
  • The Patented Solution: The invention proposes a method and architecture for controlling background operations, such as refresh, on a sectional basis. By dividing the memory array into multiple sections (e.g., quadrants), the invention allows the periphery circuits for specific sections to be activated for refresh while the circuits for other sections remain inactive. This selective control is managed through programmable address signals that target only the desired memory sections for the background operation (’960 Patent, Abstract; col. 2:36-44).
  • Technical Importance: This architecture enables a more granular power management strategy for DRAM, which may significantly reduce standby power consumption in battery-powered devices where retaining the entire memory content is not always necessary (’960 Patent, col. 2:30-34).

Key Claims at a Glance

  • The complaint asserts independent claims 1 and 27 (Compl. ¶20).
  • The essential elements of independent claim 1 include:
    • A method for reducing power consumption during background operations in a memory array with multiple sections.
    • Controlling said background operations in each section in response to one or more control signals.
    • The control signals are generated in response to a programmable address signal.
    • The background operations can be enabled simultaneously in two or more sections independently of any other section.
    • Presenting the control and decoded address signals to the periphery array circuits of the sections.
  • The complaint reserves the right to assert dependent claims from the asserted range of claims 1-27 (Compl. ¶20).

III. The Accused Instrumentality

Product Identification

  • The complaint broadly identifies two categories of accused instrumentalities:
    1. Accused DDR Memory: Any memory device that complies with the JEDEC industry standards for DDR2, DDR3, DDR4, LPDDR3, LPDDR4, LPDDR4X, and LPDDR5 (Compl. ¶8, ¶16).
    2. Accused Computing Device: Any computing device incorporating the Accused DDR Memory, including servers, desktop computers, laptops, and tablets (Compl. ¶10, ¶18).

Functionality and Market Context

  • The complaint alleges that Defendant Rubrik has used Accused Computing Devices in its business operations, specifically identifying laptop computers, desktop computers, and computer servers (Compl. ¶21-22). The infringement allegations are not tied to a specific Rubrik product but rather to the underlying standards-compliant memory components within the hardware it operates (Compl. ¶9, ¶17). The complaint does not describe the specific functionality of these devices beyond their inclusion of the accused memory.

Visual Evidence

  • No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references exemplary claim charts in Exhibits A and B, but these exhibits were not attached to the filing. The infringement theory is therefore summarized from the complaint’s narrative allegations.

’046 Patent Infringement Allegations

The complaint’s theory of infringement is that memory devices compliant with various DDR industry standards, such as the DDR4 technical specification, necessarily practice the invention claimed in the ’046 Patent (Compl. ¶8-9). The core allegation is that the architecture required by these standards for high-performance data access—which involves fetching multiple data words to service read requests—maps onto the elements of claims 1-19 (Compl. ¶12).

’960 Patent Infringement Allegations

The complaint alleges that the same Accused DDR Memory devices infringe the ’960 Patent because the methods they employ to reduce power consumption during background operations are covered by claims 1-27 (Compl. ¶15-17, ¶20). The infringement theory relies on mapping features described in DDR technical specifications, likely related to partial-array self-refresh modes, to the claimed method of independently controlling background operations in different sections of the memory array (Compl. ¶17).

  • Identified Points of Contention:
    • Scope Questions: A central dispute may be whether compliance with a JEDEC standard is sufficient to establish infringement. The analysis could raise the question of whether the features described in the standards are mandatory and, if so, whether their implementation is identical to the architecture recited in the claims. For instance, does the term "retrieving... from the memory array," as used in the ’046 Patent, read on the prefetch buffer mechanisms common in DDR memory?
    • Technical Questions: For the ’046 Patent, a key question is what evidence demonstrates that standard DDR memory performs two separate retrievals from the memory array in two distinct clock cycles, as claim 1 may be construed to require. For the ’960 Patent, the analysis will question what evidence shows that the control over refresh operations in different memory sections in standard DDR products is truly "independently of any other section," as opposed to being centrally managed with selective masking.

V. Key Claim Terms for Construction

  • The Term: "retrieving... from the memory array" (’046 Patent, Claim 1)
  • Context and Importance: This term is critical because its definition will determine whether the prefetch architectures used in modern DDR memory—where a burst of data is read from the array into a buffer in one operation before being clocked out sequentially—falls within the claim scope. Practitioners may focus on this term because the dispute could hinge on whether "retrieving" refers to the initial internal access to the memory cells or the subsequent external output of data words.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The abstract states the circuit is capable of "retrieving more than one data word in a clock cycle where the memory array is accessed," suggesting "retrieving" can refer to a single, multi-word access event (’046 Patent, Abstract).
    • Evidence for a Narrower Interpretation: The language of claim 1 recites "retrieving a first data word... in a first clock cycle and a second data word... in a second clock cycle," which could be argued to require two distinct access events to the memory array itself, each in a separate clock cycle (’046 Patent, col. 100:10-15).
  • The Term: "controlling said background operations in each of said plurality of sections... independently of any other section" (’960 Patent, Claim 1)
  • Context and Importance: The infringement case for the ’960 patent depends on whether the power-saving refresh modes in standard DDR memory (e.g., Partial Array Self-Refresh) meet this "independently" controlled limitation. The construction will be pivotal, as a narrow definition requiring complete operational autonomy for each section might exclude architectures that use a central controller to manage refresh, even if some sections are inactive.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The background section discusses the goal of refreshing "only the memory cells containing data to be retained," which supports a functional interpretation where any method that successfully isolates refresh activity to a subset of the array meets the claim’s objective (’960 Patent, col. 1:46-49).
    • Evidence for a Narrower Interpretation: The claim’s use of "independently of any other section" could be construed to require decentralized control logic for each section. The patent describes using a refresh address register to select which portion of the array is active, which a defendant may characterize as a form of centralized, rather than independent, control (’960 Patent, col. 2:1-14).

VI. Other Allegations

  • Indirect Infringement: The complaint makes no allegations of indirect infringement but explicitly reserves the right to amend the complaint to add such claims if discovery reveals pre-suit knowledge by the Defendant (Compl. p. 3, fn. 1; p. 4, fn. 2).
  • Willful Infringement: The complaint makes no allegations of willful infringement but reserves the right to add such claims upon discovery of pre-suit knowledge (Compl. p. 3, fn. 1; p. 4, fn. 2).

VII. Analyst’s Conclusion: Key Questions for the Case

The resolution of this dispute may turn on the following central questions:

  1. A primary issue will be one of standards-based infringement: can the plaintiff successfully argue that compliance with the broad and complex JEDEC DDR standards constitutes a per se implementation of the specific patented technologies, or will the defendant demonstrate that the standards permit non-infringing designs or that the accused products use such alternative implementations?
  2. A key question of claim construction and technical scope will be dispositive. For the ’046 patent: does the term "retrieving... from the memory array" in separate clock cycles encompass the common industry practice of using a single internal burst-read into a prefetch buffer? For the ’960 patent: does "controlling... independently" read on standardized partial-refresh modes that may rely on a centralized controller to deactivate, rather than independently operate, memory sections?