DCT

6:23-cv-00878

Acqis LLC v. Fujitsu Ltd.

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:23-cv-00878, W.D. Tex., 12/22/2023
  • Venue Allegations: Venue is alleged to be proper because the Defendant is a foreign corporation that does not reside in the United States, and thus may be sued in any judicial district pursuant to 28 U.S.C. § 1391(c)(3).
  • Core Dispute: Plaintiff alleges that Defendant’s laptop, desktop, and server computer products infringe ten U.S. patents related to high-speed, low-power serial data transmission technologies for computer interconnections.
  • Technical Context: The technology concerns the replacement of traditional parallel computer buses (like PCI) with serial, low-voltage differential signal (LVDS) channels to increase data transmission speeds while reducing power, noise, and physical connector size.
  • Key Procedural History: The complaint alleges that Plaintiff provided Defendant with actual notice of infringement of the patents-in-suit on or around May 15, 2018. It also references a prior 2009 patent infringement lawsuit brought by Plaintiff against Defendant’s subsidiary, Fujitsu America, Inc., involving related patents, which ended in a 2010 settlement.

Case Timeline

Date Event
1999-05-14 Earliest Priority Date for ’768, ’750, ’359, ’977, ’797, ’140, ’654, and ’436 Patents
2005-02-10 Earliest Priority Date for ’739 Patent
2005-03-31 Earliest Priority Date for ’769 Patent
2009-04-02 Plaintiff ACQIS filed suit against Fujitsu America, Inc. in E.D. Tex.
2010-06-14 ACQIS and Fujitsu America, Inc. settled prior litigation
2012-07-31 U.S. Patent No. 8,234,436 Issues
2013-12-17 U.S. Patent No. RE44,654 Issues
2014-01-07 U.S. Patent No. 8,626,977 Issues
2014-01-28 U.S. Patent No. RE44,739 Issues
2014-06-17 U.S. Patent No. 8,756,359 Issues
2014-09-16 U.S. Patent No. RE45,140 Issues
2015-03-10 U.S. Patent No. 8,977,797 Issues
2016-12-27 U.S. Patent Nos. 9,529,768 and 9,529,769 Issue
2017-07-11 U.S. Patent No. 9,703,750 Issues
2017-12-05 Accused PRIMERGY TX1310 M3 server available (on or before this date)
2018-04-03 Accused Lifebook U758 laptop available (on or before this date)
2018-04-09 Accused ESPRIMO D957/E94+ desktop available (on or before this date)
2018-05-15 Plaintiff ACQIS provided Defendant actual notice of infringement of the patents-in-suit (on or around this date)
2023-12-22 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,529,768 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions"

  • Patent Identification: U.S. Patent No. 9,529,768, "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions," issued December 27, 2016.

The Invention Explained

  • Problem Addressed: The patent describes that traditional interconnections for computer modules, such as those using the Peripheral Component Interconnect (PCI) bus standard, relied on parallel data transmission over a large number of signal channels and connector pins (Compl. ¶30). This architecture was described as consuming significant power, generating electrical noise, and being ill-suited for the small, scalable, and "cable friendly" connections needed for portable computer modules (Compl. ¶30).
  • The Patented Solution: The invention proposes replacing the high-pin-count parallel bus with a Low Voltage Differential Signal (LVDS) channel that communicates the same PCI bus transaction data serially (Compl. ¶30). As described in the patent, this serial channel uses pairs of unidirectional differential signal lines to transmit data in opposite directions, thereby reducing pin count and power consumption while increasing data transfer speeds (’436 Patent, col. 4:1-12). This approach enables more power-efficient, high-performing, and scalable interconnection systems (Compl. ¶30).
  • Technical Importance: This technological approach of serializing a parallel bus protocol over LVDS channels was a key development that enabled modern high-speed interconnects like PCI Express (PCIe) and USB 3.x (Compl. ¶¶45, 49).

Key Claims at a Glance

  • The complaint asserts independent claim 13.
  • The essential elements of claim 13 are:
    • A computer comprising:
    • an integrated central processing unit (CPU) and interface controller in a single chip;
    • a first LVDS channel directly extending from the interface controller to convey address and data bits of a PCI bus transaction in a serial bit stream, wherein the first LVDS channel comprises first unidirectional, multiple, differential signal pairs to convey data in a first direction and second unidirectional, multiple, differential signal pairs to convey data in a second, opposite direction; and
    • system memory directly coupled to the integrated CPU and interface controller.
  • The complaint reserves the right to assert additional claims (Compl. ¶133).

U.S. Patent No. 9,703,750 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions"

  • Patent Identification: U.S. Patent No. 9,703,750, "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions," issued July 11, 2017.

The Invention Explained

  • Problem Addressed: The technical problem is identical to that described for the ’768 Patent: the limitations of parallel PCI bus architectures in terms of pin count, power consumption, noise, and scalability, particularly for modular and portable computing applications (Compl. ¶30).
  • The Patented Solution: The solution is also consistent with the ’768 Patent, involving the use of an LVDS channel to serially transmit the components of a PCI bus transaction using bidirectional pairs of unidirectional signal paths (’977 Patent, Abstract). This specific patent family member focuses on a system where a CPU and an interface controller are integrated into a single chip, from which the LVDS channel directly extends (’977 Patent, col. 8:1-40).
  • Technical Importance: This architecture is presented as a foundational element adopted by industry standards such as PCI Express, which uses a "high speed, low voltage, differential serial pathway... by implementing dual unidirectional paths between two devices" (Compl. ¶45).

Key Claims at a Glance

  • The complaint asserts independent claim 1.
  • The essential elements of claim 1 are:
    • A computer comprising:
    • an integrated central processing unit (CPU) and interface controller in a single chip;
    • a first LVDS channel directly extending from the interface controller to convey address bits, data bits, and byte enable information bits of a PCI bus transaction in a serial bit stream, wherein the first LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; and
    • system memory directly coupled to the integrated CPU and interface controller.
  • The complaint reserves the right to assert additional claims (Compl. ¶149).

U.S. Patent No. 8,756,359 - "Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits"

  • Patent Identification: ’359 Patent, "Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits," issued June 17, 2014.
  • Technology Synopsis: This patent addresses improving data communication between a computer's CPU and an external console. The solution involves using a first LVDS channel directly extending from the CPU for high-speed internal data (like PCIe) and a second LVDS channel to couple to the console for external data (like USB), both using bidirectional serial transmission.
  • Asserted Claims: Independent claim 6 is asserted (Compl. ¶163).
  • Accused Features: The accused products allegedly have Intel processors (CPUs) with direct connections to internal LVDS channels (PCIe, USB 3.x) and external connectors (USB-C) that also use LVDS channels to convey data packets in opposite directions (Compl. ¶¶163(d)-(e), 166(d)-(e), 169(d)-(e)).

U.S. Patent No. 8,626,977 - "Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits"

  • Patent Identification: ’977 Patent, "Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits," issued January 7, 2014.
  • Technology Synopsis: This patent claims a computer system with a CPU and graphics subsystem integrated on a single chip. The invention describes multiple serial bit channels extending from this integrated chip to handle different data types: one LVDS channel for PCI bus transactions, another for USB protocol data, and a third for outputting digital video signals.
  • Asserted Claims: Independent claim 1 is asserted (Compl. ¶179).
  • Accused Features: The accused products allegedly feature Intel processors with an integrated CPU and graphics subsystem. These processors are accused of having LVDS channels for PCIe transactions, serial bit channels for USB 3.x data via USB-C ports, and outputs for digital video display signals (DDI/eDP) (Compl. ¶¶179(c)-(f)).

U.S. Reissue Patent No. RE44,739 - "Data Security Method and Device for Computer Modules"

  • Patent Identification: ’739 Patent, "Data Security Method and Device for Computer Modules," issued January 28, 2014.
  • Technology Synopsis: This patent focuses on a computer architecture with an integrated CPU and graphics controller. It claims a system with a first differential signal channel for digital video and a second LVDS channel for transmitting data like USB protocol packets in opposite directions to an external console via connectors.
  • Asserted Claims: Independent claim 18 is asserted (Compl. ¶192).
  • Accused Features: The accused products allegedly have Intel processors with integrated CPU and graphics controllers directly coupled to channels for digital video (eDP/DDI) and second LVDS channels for USB 3.x data that connect to external consoles via USB-C ports (Compl. ¶¶192(b)-(e)).

U.S. Patent No. 8,977,797 - "Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel"

  • Patent Identification: ’797 Patent, "Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel," issued March 10, 2015.
  • Technology Synopsis: This patent claims a method of manufacturing a computer motherboard to improve data throughput. The method involves mounting an integrated CPU and interface controller on the board and connecting an LVDS channel with multiple differential signal line pairs directly to that controller to convey PCI bus transactions in serial form.
  • Asserted Claims: Method claim 36 is asserted (Compl. ¶206).
  • Accused Features: The complaint alleges that the manufacturing process for the Accused Products necessarily performs the claimed method steps, including mounting an integrated Intel processor on a motherboard and connecting it to LVDS channels like PCIe and OPI (On-Package Interface) (Compl. ¶¶206(b)-(d)).

U.S. Patent No. 9,529,769 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction In Opposite Directions"

  • Patent Identification: ’769 Patent, "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction In Opposite Directions," issued December 27, 2016.
  • Technology Synopsis: This patent claims a method of improving external peripheral data communication. The method includes obtaining an integrated CPU/graphics controller, connecting a channel for digital video data, and providing a connector with an LVDS channel to convey USB protocol data using bidirectional serial channels.
  • Asserted Claims: Method claim 19 is asserted (Compl. ¶222).
  • Accused Features: The manufacturing process of the Accused Laptops and Desktops is alleged to include obtaining an integrated Intel processor, connecting it to video output channels (eDP/DDI), and providing a USB-C connector to convey USB 3.x data via an LVDS channel (Compl. ¶¶222(b)-(e)).

U.S. Reissue Patent No. RE45,140 - "Data Security Method and Device for Computer Modules"

  • Patent Identification: ’140 Patent, "Data Security Method and Device for Computer Modules," issued September 16, 2014.
  • Technology Synopsis: This patent claims a method for improving computer performance by manufacturing a system with an integrated CPU/graphics controller. The method involves connecting LVDS channels for both internal data (e.g., PCIe/OPI) and external peripheral data (e.g., USB 3.x), as well as a separate channel for digital video output.
  • Asserted Claims: Method claim 35 is asserted (Compl. ¶236).
  • Accused Features: The manufacturing process of the Accused Laptops is alleged to involve obtaining an integrated Intel processor, connecting it to LVDS channels for PCIe/OPI and USB 3.x data, and connecting a separate channel for digital video output (DDI/eDP) (Compl. ¶¶236(b)-(f)).

U.S. Reissue Patent No. RE44,654 - "Data Security Method and Device for Computer Modules"

  • Patent Identification: ’654 Patent, "Data Security Method and Device for Computer Modules," issued December 17, 2013.
  • Technology Synopsis: This patent claims a method of increasing data communication speed by connecting a CPU directly to a peripheral bridge (like a PCH) on a circuit board. An LVDS channel is then connected to this bridge to transmit data serially in opposite directions, and a second LVDS channel connects to a console to transmit USB data.
  • Asserted Claims: Method claim 23 is asserted (Compl. ¶250).
  • Accused Features: The manufacturing process for the Accused Products allegedly involves connecting an Intel CPU directly to a peripheral bridge (PCH) via an OPI connection, with PCIe and OPI channels connected to the PCH, and providing USB-C ports for console connection (Compl. ¶¶250(b)-(e)).

U.S. Patent No. 8,234,436 - "Computer System Including Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits"

  • Patent Identification: ’436 Patent, "Computer System Including Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits," issued July 31, 2012.
  • Technology Synopsis: This patent claims a computer with an integrated CPU and peripheral controller on a single chip. The system includes a first LVDS channel with at least two sets of unidirectional serial channels (e.g., PCIe/OPI), system memory, a mass storage device, and a second LVDS channel for digital video data directly coupled to the integrated CPU.
  • Asserted Claims: Independent claim 13 is asserted (Compl. ¶266).
  • Accused Features: The Accused Products are alleged to have integrated Intel processors with peripheral controllers, PCIe/OPI channels, directly coupled memory and SSDs, and a second LVDS channel for digital video (eDP/DDI) (Compl. ¶¶266(b)-(f)).

III. The Accused Instrumentality

  • Product Identification: The accused instrumentalities are computer products sold by Fujitsu, categorized as "Accused Laptops" (e.g., Lifebook, Stylistic), "Accused Desktops" (e.g., ESPRIMO), and "Accused Servers" (e.g., PRIMERGY series) (Compl. ¶¶58-60). The complaint provides the Fujitsu Lifebook U758, ESPRIMO D957/E94+, and PRIMERGY TX1310 M3 as representative examples (Compl. ¶¶67, 82, 97).
  • Functionality and Market Context: The complaint alleges that the accused products incorporate Intel processors (such as the 7th Generation "Kaby Lake" family or Xeon equivalents) that integrate a central processing unit (CPU), graphics subsystem, and interface controllers onto a single chip (Compl. ¶¶71, 86, 99). These products are alleged to utilize various Low Voltage Differential Signal (LVDS) channels, such as PCI Express (PCIe), USB 3.x, Direct Media Interface (DMI), and On-Package Interface (OPI), to communicate data serially using pairs of unidirectional lanes (Compl. ¶¶73-75, 88-90, 102-103). The complaint presents a block diagram from an Intel datasheet, which shows the processor's connections to system memory, storage drives, and various I/O ports, as evidence of the accused architecture (Compl. p. 23). This architecture is alleged to improve computer speed and efficiency through faster interconnections (Compl. ¶43).

IV. Analysis of Infringement Allegations

9,529,768 Patent Infringement Allegations

Claim Element (from Independent Claim 13) Alleged Infringing Functionality Complaint Citation Patent Citation
A computer The exemplary Lifebook U758 is a computer. ¶131(a) col. 3:58-65
comprising an integrated central processing unit (CPU) and interface controller in a single chip The Lifebook U758 uses a 7th Generation Intel® Core™ i5 (“Kaby Lake”) Processor, which allegedly integrates a CPU and interface controllers for driving PCIe channels onto a single chip. ¶131(b) col. 8:1-40
a first LVDS channel directly extending from the interface controller to convey address and data bits of a PCI bus transaction in a serial bit stream, wherein the first LVDS channel comprises first unidirectional, multiple... pairs... The accused Intel processors are alleged to include PCIe channels that extend directly from the integrated interface controller. The complaint alleges that PCIe is an LVDS channel that conveys PCI bus transaction data serially using pairs of unidirectional differential signal paths for opposite-direction data flow. ¶131(c) col. 4:1-12
and system memory directly coupled to the integrated CPU and interface controller. The accused processors are directly coupled to DDR4 system memory. An Intel block diagram is provided as evidence of this direct coupling (Compl. p. 29). ¶131(d) col. 8:1-40

9,703,750 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A computer The exemplary Lifebook U758 is a computer. ¶147(a) col. 3:58-65
comprising an integrated central processing unit (CPU) and interface controller in a single chip The Lifebook U758 uses a 7th Generation Intel® Core™ i5 (“Kaby Lake”) Processor, which is alleged to contain both a CPU and interface controllers on a single integrated chip. ¶147(b) col. 8:1-40
a first LVDS channel directly extending from the interface controller to convey address bits, data bits, and byte enable information bits of a PCI bus transaction in a serial bit stream, wherein the first LVDS channel comprises a first... and a second... pair The accused processors allegedly include numerous PCIe channels extending directly from the interface controller. The complaint alleges that PCIe is an implementation of an LVDS channel that conveys PCI bus transaction data—including address, data, and byte enable bits—serially using pairs of unidirectional differential signal paths for opposite-direction data flow. ¶147(c) col. 4:1-12
and system memory directly coupled to the integrated CPU and interface controller. The accused processors are directly coupled to DDR4 system memory. A block diagram from Intel is referenced to show the direct connection between the CPU and system memory (Compl. p. 29). ¶147(d) col. 8:1-40

Identified Points of Contention

  • Scope Questions: A central dispute may arise over whether the term "LVDS channel," as understood in patents with a 1999 priority date, can be construed to read on standardized, post-invention technologies like PCI Express and USB 3.x. The complaint presents these standards as embodiments of the patented invention (Compl. ¶¶45, 49), a characterization a defendant might contest by highlighting technical differences and separate development histories.
  • Technical Questions: The infringement theory hinges on mapping the patent's "integrated... CPU and interface controller in a single chip" to the architecture of modern Intel SoCs. This raises the question of what evidence supports the assertion that the functions performed by an Intel Platform Controller Hub (PCH), which is connected to the CPU die via an On-Package Interface (OPI) in some accused products (Compl. ¶¶73, 78), constitute an "interface controller" that is integrated "in a single chip" with the CPU as required by the claims.

V. Key Claim Terms for Construction

The Term: "LVDS channel"

  • Context and Importance: The construction of this term is critical, as it determines whether modern, standardized serial interconnects like PCIe, USB 3.x, and DMI fall within the scope of the claims. Practitioners may focus on this term because the complaint's infringement theory equates these well-known standards with the claimed "LVDS channel."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification states, "The term LVDS is herein used to generically refer to low voltage differential signals and is not intended to be limited to any particular type of LVDS technology" (’436 Patent, col. 4:1-4). This language may support an argument that the term should be interpreted broadly to cover various implementations of low-voltage differential signaling.
    • Evidence for a Narrower Interpretation: The patent frequently discusses the "LVDS channel" in the specific context of replacing a parallel PCI bus (’436 Patent, col. 3:8-14, Abstract). A defendant may argue that the term is implicitly limited to the specific "XPBus" embodiment and associated signaling protocols (e.g., PCK, PCKR) detailed in the specification and figures, which differ from the protocols of PCIe or USB.

The Term: "interface controller in a single chip"

  • Context and Importance: This term's definition is central to determining whether the architecture of the accused Intel processors meets the claim limitations. Practitioners may focus on this term because modern SoCs have complex, multi-part structures, and infringement depends on mapping the claimed integrated "interface controller" onto this architecture.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent describes embodiments where the host interface controller (HIC) and the north bridge are integrated, and where the peripheral interface controller (PIC) and the south bridge are integrated (’977 Patent, Fig. 8). This suggests the term "interface controller" can encompass the functions of standard chipset components.
    • Evidence for a Narrower Interpretation: The detailed description distinguishes between a "host interface controller (HIC)" and a "peripheral interface controller (PIC)" as separate components that bridge two PCI buses (’977 Patent, col. 16:1-15). This could support an argument that the claim requires a specific type of bridging controller, rather than the general-purpose I/O hub functions of a modern PCH.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement by asserting that Fujitsu provides instructions to end users on how to use the Accused Products and has configured them such that "direct infringing use necessarily occurs upon operation... in their normal, intended manner" (Compl. ¶126).
  • Willful Infringement: Willfulness is alleged based on both pre-suit and post-suit knowledge. The complaint alleges pre-suit knowledge stemming from a 2009 lawsuit against Fujitsu America, Inc. that settled in 2010, and an actual notice letter sent on or around May 15, 2018, that identified the asserted patents and accused products (Compl. ¶¶112, 115, 121). Continued infringement after receiving this notice is alleged to be willful (Compl. ¶118).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can the term "LVDS channel," as defined in patents with a 1999 priority date and specific "XPBus" embodiments, be construed broadly enough to encompass distinct, industry-standardized protocols such as PCI Express and USB 3.x that were developed after the priority date?
  • A key technical question will be one of architectural mapping: does the structure of the accused multi-component Intel processors, which in some cases integrate a CPU and a Platform Controller Hub (PCH) on the same package connected by an OPI, meet the claim limitation of an "interface controller in a single chip" with a "directly extending" channel, or is there a functional and structural mismatch with the architecture disclosed in the patents?
  • A key factual issue for damages will be willfulness: what level of knowledge can be imputed to the Japanese parent company, Fujitsu Limited, from a 2010 settlement involving its U.S. subsidiary and a 2018 notice letter, and did its subsequent conduct rise to the level of egregious behavior required for enhanced damages?