6:23-cv-00880
Acqis LLC v. Panasonic Holdings Corp.
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Acqis LLC (Texas)
- Defendant: Panasonic Holdings Corporation (Japan) and Panasonic Corporation of North America (Delaware)
- Plaintiff’s Counsel: Scott Douglass & McConnico LLP; Dorsey & Whitney LLP
- Case Identification: 6:23-cv-00880, W.D. Tex., 12/22/2023
- Venue Allegations: Plaintiff alleges venue is proper because Defendant Panasonic Holdings Corporation is a foreign entity that may be sued in any judicial district. Venue is also alleged to be proper for Defendant Panasonic Corporation of North America based on its regular and established places of business within the district, specifically in Round Rock and El Paso, Texas. The complaint also asserts that judicial efficiency favors this venue due to other pending cases in the district involving the same patents.
- Core Dispute: Plaintiff alleges that Defendant’s Toughbook laptops and Toughpad tablets infringe nine patents related to high-speed, serial data transmission technologies, particularly those employing Low Voltage Differential Signal (LVDS) channels to communicate information for protocols like PCI Express and USB.
- Technical Context: The technology concerns foundational methods for increasing the speed and power efficiency of data interconnections within computer systems by replacing wide, parallel buses with high-speed, bidirectional serial links.
- Key Procedural History: The complaint alleges that Plaintiff provided Defendant with actual notice of infringement of all asserted patents on or around May 15, 2018, via a letter that identified the accused product lines. The complaint also notes that the asserted patents have been the subject of prior litigation in the same district against other technology companies, with a trial in one such case scheduled for March 2024.
Case Timeline
| Date | Event |
|---|---|
| 1999-05-14 | Earliest Priority Date for eight of the nine patents-in-suit |
| 2005-02-10 | Earliest Priority Date for U.S. Patent No. RE44,739 |
| 2012-07-31 | U.S. Patent No. 8,234,436 Issues |
| 2013-12-17 | U.S. Patent No. RE44,654 Issues |
| 2014-01-07 | U.S. Patent No. 8,626,977 Issues |
| 2014-01-28 | U.S. Patent No. RE44,739 Issues |
| 2014-06-17 | U.S. Patent No. 8,756,359 Issues |
| 2014-09-16 | U.S. Patent No. RE45,140 Issues |
| 2015-03-10 | U.S. Patent No. 8,977,797 Issues |
| 2016-12-27 | U.S. Patent No. 9,529,768 Issues |
| 2017-01-01 | Defendant allegedly begins selling accused products in Texas |
| 2017-07-11 | U.S. Patent No. 9,703,750 Issues |
| 2018-05-15 | Plaintiff allegedly provides Defendant with actual notice of infringement |
| 2023-12-22 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,529,768 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions"
The Invention Explained
- Problem Addressed: The patent's background describes the technical challenge that traditional computer interconnections, such as the Peripheral Component Interconnect (PCI) bus, used wide parallel data paths with a high number of connector pins, which made them power-inefficient, noisy, and unsuitable for scalable, "cable friendly" applications. (Compl. ¶39; ’768 Patent, col. 3:40-67).
- The Patented Solution: The invention proposes a computer system architecture where a central processing unit (CPU) or a peripheral bridge is connected directly to a Low Voltage Differential Signal (LVDS) channel. This channel uses pairs of unidirectional, differential signal lines to transmit the address and data bits of a PCI bus transaction as a serial bit stream, with data flowing in opposite directions simultaneously. (’768 Patent, Abstract; ’768 Patent, col. 5:1-19). This reduces pin count, lowers power consumption, and enables higher data speeds over longer distances.
- Technical Importance: This serial, differential signaling approach became a foundational principle for modern high-speed interconnect standards like PCI Express (PCIe) and Universal Serial Bus (USB) 3.x, which replaced legacy parallel buses. (Compl. ¶¶52-53).
Key Claims at a Glance
- The complaint asserts at least independent claim 13. (Compl. ¶120).
- The essential elements of claim 13 are:
- A computer comprising:
- an integrated central processing unit (CPU) and interface controller in a single chip;
- a first low voltage differential signal (LVDS) channel directly extending from the interface controller to convey address and data bits of a peripheral component interconnect (PCI) bus transaction in a serial bit stream, wherein the first LVDS channel comprises first unidirectional, multiple, differential signal pairs to convey data in a first direction and second unidirectional, multiple, differential signal pairs to convey data in a second, opposite direction; and
- system memory directly coupled to the integrated CPU and interface controller.
- The complaint explicitly reserves the right to assert additional claims. (Compl. ¶122).
U.S. Patent No. 9,703,750 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions"
The Invention Explained
- Problem Addressed: The patent addresses the same technical problem as the '768 Patent: the inefficiency and physical limitations of parallel bus architectures (like PCI) for connecting computer components, which hindered the adoption of more efficient LVDS-based serial communication. (Compl. ¶39; ’750 Patent, col. 3:40-67).
- The Patented Solution: The invention claims a method of manufacturing a computer to improve data communication. The method involves obtaining a single chip containing an integrated CPU and graphics controller and directly connecting a differential signal channel to it. This channel is then used in conjunction with a connector to convey USB protocol data serially using two unidirectional channels for simultaneous bidirectional communication. (’750 Patent, Abstract; ’750 Patent, col. 5:1-19).
- Technical Importance: This manufacturing method enabled the integration of high-speed external interfaces like USB 3.x, which rely on the patented serial, bidirectional LVDS-based communication architecture, directly into the core processor logic of a computer. (Compl. ¶57).
Key Claims at a Glance
- The complaint asserts at least independent claim 50. (Compl. ¶134).
- The essential elements of claim 50 are:
- A method of improving external peripheral data communication of a computer, comprising:
- obtaining an integrated central processing unit (CPU) and graphics controller as a single chip;
- connecting a first unidirectional, differential signal pair channel directly to the integrated CPU and graphics controller;
- providing a connector for external peripheral data communication; and
- providing an LVDS channel to convey USB protocol data through the connector that uses two unidirectional, serial bit channels that transmit data in opposite directions.
- The complaint explicitly reserves the right to assert additional claims. (Compl. ¶136).
U.S. Patent No. 8,756,359 - "Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits"
Technology Synopsis
The patent describes a computer system with a CPU directly connected to LVDS channels. These channels facilitate communication with external consoles via connectors (e.g., USB 3.x ports) by conveying protocol data packets using pairs of unidirectional, differential signal paths.
Asserted Claims
At least independent claim 6 is asserted. (Compl. ¶147).
Accused Features
The accused products allegedly meet the claim limitations through their Intel Core processors (CPU) that have directly extending PCIe and USB 3.x channels (first LVDS channel) and USB 3.x ports (second LVDS channel) for connecting to consoles. (Compl. ¶¶147, 150).
U.S. Patent No. 8,626,977 - "Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits"
Technology Synopsis
This patent claims a computer system with an integrated single-chip CPU and graphics subsystem. The system uses LVDS channels extending directly from the CPU to transmit PCI bus transactions serially and bidirectionally, as well as separate serial bit channels for conveying USB protocol data.
Asserted Claims
At least independent claim 1 is asserted. (Compl. ¶160).
Accused Features
The infringement allegation centers on the accused products' use of Intel processors with integrated CPU/graphics, which allegedly have LVDS channels (PCIe) for PCI transactions and serial bit channels for USB 3.x data, and output digital video signals. (Compl. ¶¶160, 163).
U.S. Patent No. RE44,739 - "Data Security Method and Device for Computer Modules"
Technology Synopsis
The patent describes a computer having an integrated single-chip CPU and graphics controller. This chip is directly coupled to a first differential signal channel for digital video and a second LVDS channel with at least two pairs of unidirectional lanes for bidirectional data transmission (e.g., USB).
Asserted Claims
At least independent claim 18 is asserted. (Compl. ¶173).
Accused Features
The accused products are alleged to infringe by using Intel processors with integrated CPU/graphics that are directly coupled to video channels (eDP/DDI) and data channels (USB 3.x). (Compl. ¶¶173, 176).
U.S. Patent No. 8,977,797 - "Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel"
Technology Synopsis
The patent claims a method for improving data throughput on a motherboard. The method involves mounting a single-chip integrated CPU and interface controller and connecting an LVDS channel directly to it, with the controller being adaptable for different numbers of differential signal line pairs to convey PCI bus transactions.
Asserted Claims
At least independent claim 36 is asserted. (Compl. ¶187).
Accused Features
The manufacture of the accused products allegedly practices the claimed method by using a motherboard with an integrated Intel CPU/interface controller that is directly connected to configurable PCIe and OPI interfaces. (Compl. ¶¶187, 190).
U.S. Patent No. RE45,140 - "Data Security Method and Device for Computer Modules"
Technology Synopsis
This patent relates to a method of improving computer performance by obtaining a single-chip integrated CPU/graphics controller and connecting various LVDS and differential signal channels to it for bidirectional data transmission (PCIe, OPI) and digital video output (DDI/eDP).
Asserted Claims
At least independent claim 35 is asserted. (Compl. ¶201).
Accused Features
The manufacture of the accused products is alleged to infringe by integrating an Intel CPU/graphics controller and connecting it to PCIe, OPI, and DDI/eDP channels and providing a USB 3.x connector. (Compl. ¶¶201, 204).
U.S. Patent No. RE44,654 - "Data Security Method and Device for Computer Modules"
Technology Synopsis
The patent claims a method of increasing data communication speed by directly connecting a CPU to a peripheral bridge (PCH) on a circuit board. An LVDS channel is connected directly to this bridge to transmit data serially and bidirectionally.
Asserted Claims
At least independent claim 23 is asserted. (Compl. ¶215).
Accused Features
The manufacturing process for the accused products allegedly infringes by connecting an Intel CPU to an Intel Platform Controller Hub (PCH) via an OPI connection, with the PCH in turn connected to PCIe/OPI channels and USB 3.x ports. (Compl. ¶¶215, 218).
U.S. Patent No. 8,234,436 - "Computer System Including Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits"
Technology Synopsis
This patent describes a computer system with a single-chip integrated CPU and peripheral controller. This chip is directly coupled to one or more LVDS channels for communicating PCI bus transactions and a second LVDS channel for conveying digital video data.
Asserted Claims
At least independent claim 13 is asserted. (Compl. ¶228).
Accused Features
The accused products are alleged to infringe by using Intel processors with an integrated controller directly coupled to PCIe/OPI channels and to eDP/DDI video channels. (Compl. ¶¶228, 231).
III. The Accused Instrumentality
Product Identification
- The accused instrumentalities are laptop and tablet computer products sold by Defendant under the brand name Toughbook, collectively referred to as the "Accused Panasonic Products." (Compl. ¶¶67-69). The complaint uses the Panasonic TOUGHBOOK 31 laptop and TOUGHPAD FZ-G1 tablet as representative examples. (Compl. ¶¶74, 89).
Functionality and Market Context
- The accused products are ruggedized computer systems that utilize 7th Generation Intel® Core™ i5 ("Kaby Lake") processors. (Compl. ¶¶76, 91). These processors are alleged to be "System-on-a-Chip" (SoC) devices that integrate a CPU, a graphics subsystem, and an interface controller onto a single chip. (Compl. ¶78). This integrated controller connects directly to various high-speed serial LVDS channels, including PCI Express (PCIe) for communication with mass storage, USB 3.x ports for external peripherals, and digital display interfaces like HDMI and eDP. (Compl. ¶¶80-82). A processor platform diagram from an Intel datasheet is provided to illustrate the SoC architecture, showing direct connections from the processor to PCIe, USB, and display interfaces. (Compl. ¶78, Fig. 1-1). The processor also allegedly contains an integrated Platform Controller Hub (PCH) die, which acts as a peripheral bridge connected to the CPU die via an On-Package Interface (OPI). (Compl. ¶85).
IV. Analysis of Infringement Allegations
U.S. Patent No. 9,529,768 Infringement Allegations
| Claim Element (from Independent Claim 13) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a computer comprising: an integrated central processing unit (CPU) and interface controller in a single chip; | The accused TOUGHBOOK 31 is a computer that uses a 7th Generation Intel® Core™ i5 Processor, which allegedly includes interface controllers and the CPU integrated as a single chip. | ¶120(a)-(b) | col. 3:56-67 |
| a first low voltage differential signal (LVDS) channel directly extending from the interface controller to convey address and data bits of a peripheral component interconnect (PCI) bus transaction in a serial bit stream, wherein the first LVDS channel comprises first unidirectional, multiple, differential signal pairs to convey data... | The Intel processor includes PCIe channels that directly extend from the integrated interface controller. These channels are alleged to be LVDS channels that convey PCI bus transaction data serially using bidirectional pairs of lanes. | ¶120(c) | col. 4:1-10 |
| ...in a first direction and second unidirectional, multiple, differential signal pairs to convey data in a second, opposite direction; and | The processor's PCIe channels allegedly use unidirectional, multiple, differential signal pairs to convey data in opposite directions. | ¶120(c) | col. 4:21-31 |
| system memory directly coupled to the integrated CPU and interface controller. | The Intel processor is directly coupled to DDR4 system memory. | ¶120(d) | col. 3:63-64 |
U.S. Patent No. 9,703,750 Infringement Allegations
| Claim Element (from Independent Claim 50) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A method of improving external peripheral data communication of a computer, the method comprising: obtaining an integrated central processing unit (CPU) and graphics controller as a single chip; | During manufacturing of the TOUGHBOOK 31, a 7th Generation Intel® Core™ i5 Processor is obtained, which is alleged to be an integrated CPU and graphics controller on a single chip. | ¶134(a)-(b) | col. 5:1-4 |
| connecting a first unidirectional, differential signal pair channel directly to the integrated CPU and graphics controller; | During manufacturing, PCIe channels are connected directly to the integrated CPU and graphics controller, which are alleged to be unidirectional, differential signal pair channels. | ¶134(c) | col. 5:5-7 |
| providing a connector for external peripheral data communication; and | The TOUGHBOOK 31 is manufactured with connectors for external peripherals, such as a USB 3.x port. | ¶134(d) | col. 5:8-9 |
| providing an LVDS channel to convey USB protocol data through the connector that uses two unidirectional, serial bit channels that transmit data in opposite directions. | The manufacturing process provides an LVDS channel (the USB 3.x port) to convey USB 3.x data using two unidirectional, serial bit channels transmitting data in opposite directions. | ¶134(e) | col. 5:10-14 |
Identified Points of Contention
- Scope Questions: A principal issue may be whether the term "peripheral component interconnect (PCI) bus transaction," as used in patents with a 1999 priority date, can be construed to read on the modern, packet-based PCIe protocol implemented in the accused products. The complaint asserts that PCIe is software backward-compatible with PCI and embodies the patented invention (Compl. ¶¶53, 55), but the underlying technical protocols are different.
- Technical Questions: The claims require various components to be "directly" connected or "directly extending from" the CPU or interface controller. The complaint's infringement theory relies on an architecture where the processor SoC contains both a CPU die and a Platform Controller Hub (PCH) die connected by an On-Package Interface (OPI) (Compl. ¶85). A question for the court will be whether this on-package, inter-die connection satisfies the "directly connected" limitation, or if the PCH constitutes an intervening component that breaks the direct connection required by the claims.
V. Key Claim Terms for Construction
The Term: "directly connected to" / "directly extending from"
Context and Importance
These terms are central to the infringement allegations, which contend that LVDS channels like PCIe and USB 3.x extend "directly" from the integrated processor chip. The physical and logical architecture of the accused Intel SoC, which may contain multiple dies (e.g., CPU and PCH) within a single package, will be scrutinized. Practitioners may focus on this term because its construction will determine whether the on-package architecture of the accused products meets a key claim limitation.
Intrinsic Evidence for Interpretation
- Evidence for a Broader Interpretation: The patents' specification may describe the invention's goal as eliminating separate, motherboard-level bridge chips that were common in the prior art. Language contrasting the invention with systems requiring distinct physical chips for I/O control could support a construction where "directly" means integrated onto the same semiconductor package or substrate, even if on a different die. The patent figures, such as Fig. 8 in the '977 Patent, depict an "Integrated Host Interface Cntlr. & North Bridge," suggesting a functional, integrated view.
- Evidence for a Narrower Interpretation: The specification may describe specific embodiments showing a direct physical trace from a single, monolithic CPU/controller block to an I/O pin. Such descriptions could support a narrower construction requiring no intervening logical blocks or inter-die interfaces, which a defendant might argue the OPI represents.
The Term: "peripheral component interconnect (PCI) bus transaction"
Context and Importance
The patents claim priority to 1999, when the parallel PCI standard was dominant. The accused products use the serial PCIe standard. The viability of the infringement case for several claims depends on construing the legacy term "PCI bus transaction" to encompass modern PCIe communications.
Intrinsic Evidence for Interpretation
- Evidence for a Broader Interpretation: The patents' background sections frame the problem as the high pin count and electrical limitations of parallel buses in general. (’768 Patent, col. 3:40-67). This context may support a construction where "PCI bus transaction" refers to the function of communicating address, data, and control information for peripheral components, a function also performed by PCIe, rather than being limited to the specific signals of the legacy PCI protocol.
- Evidence for a Narrower Interpretation: The specification may define or describe the "PCI bus transaction" by referencing specific signals of the parallel PCI 2.x standard, such as FRAME#, IRDY#, and DEVSEL#. (’977 Patent, col. 19:1-25). Such explicit references could be used to argue that the claim term is limited to the specific legacy protocol and does not read on the packet-based, signal-less protocol of PCIe.
VI. Other Allegations
Indirect Infringement
- The complaint alleges that Defendant induces infringement by actively promoting and advertising the accused products for the U.S. market, providing instruction manuals that direct users to operate the products in an infringing manner, and configuring the products such that their normal, intended operation necessarily infringes. (Compl. ¶¶112, 115).
Willful Infringement
- Willfulness is alleged based on Defendant’s purported actual notice of the patents-in-suit. The complaint claims that on May 15, 2018, Plaintiff sent a letter to Defendant identifying the asserted patents and the accused product lines (Toughbook and Toughpad), but that Defendant continued its alleged infringement. (Compl. ¶¶104-108, 110).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of technological translation: can the term "PCI bus transaction," defined by the parallel bus architecture of the late 1990s, be construed to encompass the fundamentally different serial, packet-based protocol of the modern PCIe standard implemented in the accused products? The outcome may depend on whether the court focuses on the literal protocol signals of the era or the broader function of peripheral interconnection.
- A key question of claim scope will be the definition of "directly connected" in the context of a multi-die System-on-a-Chip (SoC). The case may turn on whether a connection between a CPU die and a PCH die within the same processor package, linked by an On-Package Interface, is considered a "direct" connection from the "single chip" as claimed, or if the PCH is an intervening peripheral bridge that negates directness.
- An evidentiary question will be what specific technical documentation reveals about the operation of the accused Intel processors. The analysis will require detailed evidence on whether the processor's integrated interface controller is configured to adapt to different numbers of differential signal line pairs and generate different clock frequencies for PCIe/USB transactions, as required by the method claims. The complaint's reliance on a PCH clocking profile screenshot suggests this will be a point of technical inquiry. (Compl. ¶86).