DCT

6:23-cv-00881

Acqis LLC v. ZT Group Int'l, Inc.

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: Acqis LLC v. ZT GROUP INT’L, INC., 6:23-cv-00881, W.D. Tex., 12/22/2023
  • Venue Allegations: Plaintiff alleges venue is proper based on Defendant’s regular and established places of business in the district, including an office in Austin and plans for a manufacturing site in Georgetown, Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s server products, which incorporate high-speed data interconnects like PCI Express, infringe six patents related to serial data transmission over low-voltage differential signal channels.
  • Technical Context: The technology concerns methods for converting parallel bus communications, such as from a CPU, into high-speed serial data streams for transmission, a foundational concept for modern I/O standards like PCI Express and USB 3.x that are critical to the data center and server industries.
  • Key Procedural History: Plaintiff alleges it provided Defendant with actual notice of infringement via letters sent on or around July 17, 2018, and September 10, 2020. The complaint also notes that certain patents-in-suit have been asserted in prior litigation within the same district, which Plaintiff cites to support judicial efficiency.

Case Timeline

Date Event
1999-05-14 Earliest Priority Date for all asserted patents
2012-07-31 U.S. Patent No. 8,234,436 Issued
2013-12-17 U.S. Patent No. RE44,654 Issued
2015-03-10 U.S. Patent No. 8,977,797 Issued
2016-12-27 U.S. Patent No. 9,529,768 Issued
2017-07-11 U.S. Patent No. 9,703,750 Issued
2018-06-16 Alleged infringing shipment of XPO200 servers by Defendant
2018-07-10 U.S. Patent No. RE46,947 Issued
2018-07-17 Plaintiff alleges providing Defendant with actual notice of infringement
2019-05-28 Alleged infringing shipment of XPO200 servers by Defendant
2019-12-01 Alleged infringing shipments of XPO200 servers by Defendant
2020-09-10 Plaintiff alleges sending a follow-up notice letter to Defendant
2023-12-22 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,529,768 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions"

The Invention Explained

  • Problem Addressed: Traditional computer interconnections for standards like the Peripheral Component Interconnect (PCI) bus relied on parallel data transmission using a large number of signal channels and connector pins (Compl. ¶34). This architecture was described as not "cable friendly" and made it difficult to employ more efficient, lower-power technologies like low-voltage differential signal (LVDS) channels (Compl. ¶34; ’436 Patent, col. 3:40-54).
  • The Patented Solution: The invention proposes a system where a CPU or peripheral bridge is directly connected to an LVDS channel. This channel converts the parallel data of a PCI bus transaction into a serial bit stream and transmits it using pairs of unidirectional, differential signal paths—one for each direction. This serialization reduces pin count and allows for higher-speed, more power-efficient data transfer over cables (’436 Patent, col. 3:55-68, Fig. 9).
  • Technical Importance: This approach provided a scalable and power-efficient method for high-speed data transfer between computer components, forming a basis for subsequent industry standards like PCI Express (PCIe), which also use high-speed, low-voltage, differential serial pathways (Compl. ¶45).

Key Claims at a Glance

  • The complaint asserts independent claim 13 and reserves the right to assert additional claims (Compl. ¶¶92, 94).
  • Claim 13 Elements:
    • A computer comprising:
    • an integrated central processing unit (CPU) and interface controller in a single chip;
    • a first LVDS channel directly extending from the interface controller to convey address and data bits of a PCI bus transaction in a serial bit stream, wherein the first LVDS channel comprises first and second unidirectional, multiple, differential signal pairs to convey data in opposite directions;
    • system memory directly coupled to the integrated CPU and interface controller.

U.S. Patent No. 9,703,750 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions"

The Invention Explained

  • Problem Addressed: As with the ’768 Patent, this patent addresses the technical limitations of parallel bus architectures, such as high pin counts and inefficiency, which hindered the use of high-speed serial interconnects (Compl. ¶34).
  • The Patented Solution: The invention describes a computer system with an integrated CPU and interface controller on a single chip. This integrated unit connects directly to an LVDS channel that serially conveys the constituent bits (address, data, and byte enable information) of a PCI bus transaction using a pair of unidirectional, differential signal paths for bidirectional communication (’436 Patent, col. 8:16-24; Fig. 9).
  • Technical Importance: The technology enabled a more compact, high-performance, and power-efficient I/O architecture by integrating the interface logic with the CPU and using a serialized transport mechanism, anticipating the architectural shift seen in standards like PCIe (Compl. ¶¶45, 47).

Key Claims at a Glance

  • The complaint asserts independent claim 1 and reserves the right to assert additional claims (Compl. ¶¶102, 104).
  • Claim 1 Elements:
    • A computer comprising:
    • an integrated CPU and interface controller in a single chip;
    • a first LVDS channel directly extending from the interface controller to convey address bits, data bits, and byte enable information bits of a PCI bus transaction in a serial bit stream, the channel comprising a first and second unidirectional, differential signal pair for data conveyance in opposite directions;
    • system memory directly coupled to the integrated CPU and interface controller.

U.S. Patent No. 8,977,797 - "Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel"

  • Technology Synopsis: This patent claims a method of manufacturing a motherboard to improve data throughput. The method involves mounting an integrated CPU and interface controller and connecting an LVDS channel directly to it, with the channel configured to carry PCI bus transaction data in serial form (Compl. ¶¶39, 113).
  • Asserted Claims: The complaint asserts at least claim 36 (Compl. ¶113).
  • Accused Features: The complaint alleges that the Accused ZT Products were manufactured using the claimed method, pointing to the integrated Intel processors, PCIe/DMI channels, and connections to peripheral devices on the motherboard (Compl. ¶113).

U.S. Patent No. RE46,947 - "Data Security Method and Device for Computer Modules"

  • Technology Synopsis: This patent, a reissue of U.S. Patent No. 6,643,777, describes a computer with an integrated CPU, a directly coupled mass storage device, and an LVDS channel extending from the CPU. The CPU is configured to output a serial bit stream containing the components of a PCI bus transaction (Compl. ¶¶41, 123).
  • Asserted Claims: The complaint asserts at least claim 19 (Compl. ¶123).
  • Accused Features: The infringement allegation centers on the accused servers' integrated Intel Xeon processors being directly coupled to an SSD and having PCIe channels that extend from an integrated interface controller (Compl. ¶123).

U.S. Patent No. RE44,654 - "Data Security Method and Device for Computer Modules"

  • Technology Synopsis: A reissue of the same original patent as the ’947 Patent, this patent claims a method of increasing data communication speed. The method includes connecting a CPU directly to a peripheral bridge, connecting an LVDS channel to that bridge, and providing a connector to link to external consoles via a second LVDS channel carrying protocol data like USB (Compl. ¶¶40, 134).
  • Asserted Claims: The complaint asserts at least claim 23 (Compl. ¶134).
  • Accused Features: The complaint alleges the accused products were manufactured using the claimed method, citing the direct CPU-to-PCH (peripheral bridge) connection via DMI and the presence of USB 3.x ports for external connection (Compl. ¶134).

U.S. Patent No. 8,234,436 - "Computer System Including Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits"

  • Technology Synopsis: This patent describes a computer with an integrated CPU and peripheral controller directly coupled to LVDS channels. The system also includes a mass storage device and a second LVDS channel for conveying digital video data from an integrated graphics controller (Compl. ¶¶42, 144).
  • Asserted Claims: The complaint asserts at least claim 13 (Compl. ¶144).
  • Accused Features: The infringement theory relies on the accused servers' integrated Intel processors being coupled to an SSD and having PCIe channels that connect the CPU to a graphics processor (GPU) (Compl. ¶144).

III. The Accused Instrumentality

Product Identification

The "Accused ZT Products" include servers sold under the brand names XPO200 Server Solutions, XPO200 3U PCIe Expansion System, XPO200 3UN PCIe, and XPO200 3UA PCIe (Compl. ¶60). The complaint uses the XPO200 3UN PCIe Expansion System ("3UN PCIe") as an illustrative example (Compl. ¶66).

Functionality and Market Context

The Accused ZT Products are described as computer servers designed for data center applications such as cloud workloads, analytics, and artificial intelligence (Compl. ¶58). The 3UN PCIe server uses up to two Intel® Xeon® ("Skylake") processors, which feature integrated interface controllers that drive PCIe channels connected to the processor (Compl. ¶68). A motherboard block diagram shows these CPUs connected to a PCH ("Lewisburg") chipset via a DMI link and directly to various PCIe slots (Compl. p. 23, Fig. 1). The server connects directly to DDR4 system memory, mass storage (NVMe SSD), and external consoles via connectors including USB 3.x ports (Compl. ¶¶69, 72, 73). A system configuration table specifies an M.2 NVMe SSD "sourced from CPU" (Compl. p. 26, Table 2). Defendant is alleged to be a "global leader in the computer server market" (Compl. ¶56).

IV. Analysis of Infringement Allegations

’768 Patent Infringement Allegations

Claim Element (from Independent Claim 13) Alleged Infringing Functionality Complaint Citation Patent Citation
a computer comprising: The 3UN PCIe is a computer. ¶92(a) ’436 Patent, col. 3:55-58
an integrated central processing unit (CPU) and interface controller in a single chip, The 3UN PCIe uses an Intel Xeon ("Skylake") Processor, which integrates the CPU and interface controllers (e.g., to drive PCIe channels) on a single chip. ¶92(b) ’436 Patent, Fig. 8B
a first LVDS channel directly extending from the interface controller to convey address and data bits of a PCI bus transaction in a serial bit stream... comprising first... and second unidirectional, multiple, differential signal pairs to convey data in... opposite direction... The Intel Xeon processors in the 3UN PCIe include PCIe channels that directly extend from the integrated interface controller and use pairs of unidirectional lanes to transmit data in opposite directions. ¶92(c) ’436 Patent, col. 16:1-21
system memory directly coupled to the integrated CPU and interface controller, The Intel Xeon processors are directly coupled to the server's DDR4 system memory. ¶92(d) ’436 Patent, Fig. 2

’750 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a computer comprising: The 3UN PCIe is a computer. ¶102(a) ’436 Patent, col. 3:55-58
an integrated central processing unit (CPU) and interface controller in a single chip; The 3UN PCIe uses an Intel Xeon ("Skylake") Processor, which integrates the CPU and interface controllers on a single chip. ¶102(b) ’436 Patent, Fig. 8B
a first LVDS channel directly extending from the interface controller to convey address bits, data bits, and byte enable information bits of a PCI bus transaction in a serial bit stream, wherein the first LVDS channel comprises a first unidirectional, differential signal pair... and a second unidirectional, differential signal pair... in a second, opposite direction, The Intel Xeon processors include numerous PCIe channels that directly extend from the integrated interface controller and utilize pairs of unidirectional differential signal lanes. ¶102(c) ’436 Patent, col. 16:1-21
system memory directly coupled to the integrated CPU and interface controller; The server's DDR3 (or DDR4) system memory is directly coupled to the integrated Intel Xeon processors. ¶102(d) ’436 Patent, Fig. 2

Identified Points of Contention

  • Scope Questions: A central dispute may concern whether the term "PCI bus transaction," rooted in the patent’s context of parallel PCI architecture from the late 1990s, can be construed to read on the serialized, packet-based data communications of the modern PCIe standard used in the accused servers. The complaint alleges that PCIe "embodies Dr. Chu's patented interconnection invention" (Compl. ¶45), framing this as a key assertion for the court.
  • Technical Questions: The infringement theory relies on the Intel Xeon processor containing an "interface controller" that meets the claim limitation. A potential point of contention is whether the distributed logic for managing PCIe lanes within the complex system-on-a-chip architecture of a modern CPU constitutes the specific "interface controller" structure described in the patents, which at times depict it as a discrete block (e.g., HIC 905 in ’436 Patent, Fig. 9).

V. Key Claim Terms for Construction

The Term: "interface controller"

  • Context and Importance: This term's construction is critical to determining whether the integrated architecture of the accused Intel Xeon processors infringes. Practitioners may focus on this term because the dispute will likely turn on whether the claimed "interface controller" must be a structurally distinct component or can be a functional block integrated within a larger system-on-a-chip.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the controller's function as encoding and decoding signals between a parallel bus and a serial channel (’436 Patent, col. 6:1-23). The patent also explicitly illustrates an "Attached Computer Module with Single Chip fully integrated: CPU, Cache, Core logic, Graphics controller and Interface controller," which may support the view that integration was contemplated (’436 Patent, Fig. 8B).
    • Evidence for a Narrower Interpretation: Several figures in the patent depict the "Host Interface Controller" (HIC) and "Peripheral Interface Controller" (PIC) as discrete blocks separate from the CPU and North Bridge (’436 Patent, Fig. 9). This could support an argument that the inventors conceived of the controller as a structurally separate component.

The Term: "PCI bus transaction"

  • Context and Importance: The definition of this term is central to whether the patents, which describe serializing a parallel bus transaction, can cover the natively serial PCIe protocol used in the accused products.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claims refer to conveying the "address and data bits" or "address bits, data bits, and byte enable information bits" of such a transaction (’768 Patent, cl. 13; ’750 Patent, cl. 1). This language may suggest that the invention is concerned with the informational content of the transaction, not its specific physical layer signaling protocol.
    • Evidence for a Narrower Interpretation: The patent's background focuses on the problems of the parallel PCI bus standard (’436 Patent, col. 3:40-44). An argument could be made that "PCI bus transaction" is a term of art limited to the specific parallel protocol known at the time of invention, and that the fundamentally different packetized protocol of PCIe falls outside its scope.

VI. Other Allegations

Willful Infringement

The complaint alleges willful infringement based on pre-suit knowledge. It states that ACQIS notified ZT Systems of the asserted patents and its infringement on or around July 17, 2018, and sent a follow-up letter on September 10, 2020 (Compl. ¶¶81, 84). The complaint alleges Defendant "ignored the notice and chose to remain willfully blind to its own infringement" and continued its accused activities (Compl. ¶86).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can the term "PCI bus transaction," which is described in the patents in the context of converting parallel bus signals, be construed to cover the natively serial, packet-based communications of the accused products' PCIe and DMI interfaces? The outcome may depend on whether the court focuses on the informational content being transferred or the specific signaling protocol used.
  • A key infringement question will be one of structural mapping: does the claimed "interface controller," depicted in patent figures as a discrete functional block, read on the integrated logic within the accused Intel Xeon system-on-a-chip that manages the PCIe data lanes? This will require a detailed analysis of both the patent's description and the accused processor's architecture.
  • An evidentiary question will center on damages and willfulness: assuming infringement is found, the allegation that Defendant had notice of the patents since July 2018, nearly four and a half years before the complaint was filed, will be central to Plaintiff's attempt to prove willful infringement and its request for enhanced damages.