DCT
6:23-cv-00882
Acqis LLC v. Advantech Co Ltd
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Acqis LLC (Texas)
- Defendant: Advantech Co., Ltd. (Taiwan)
- Plaintiff’s Counsel: Scott Douglass & McConnico LLP; Dorsey & Whitney LLP
- Case Identification: 6:23-cv-00882, W.D. Tex., 12/22/2023
- Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign corporation not resident in the United States and may be sued in any judicial district. Plaintiff further argues for venue based on judicial efficiency, noting that the asserted patents have been previously litigated in this District.
- Core Dispute: Plaintiff alleges that Defendant’s computer servers, motherboards, and single-board computers, which utilize serial data transmission standards like PCI Express and USB 3.x, are manufactured abroad using methods that infringe five U.S. patents related to high-performance, low-power computer interconnection technologies.
- Technical Context: The patents relate to foundational methods for replacing older, parallel data buses (like PCI) with high-speed, low-voltage differential signal (LVDS) serial channels to connect core computer components, a technology paradigm now central to modern computing.
- Key Procedural History: The complaint alleges that Plaintiff provided Defendant with notice of its patent portfolio and likely infringement on or around April 30, 2013, a fact which forms the basis for the willful infringement allegation.
Case Timeline
| Date | Event |
|---|---|
| 1999-05-14 | Earliest Priority Date for ’750, ’797, ’140, ’654 Patents |
| 2005-03-31 | Priority Date for ’769 Patent |
| 2013-04-30 | Plaintiff allegedly provided notice of infringement to Defendant |
| 2013-12-17 | ’654 Patent Issue Date |
| 2014-09-16 | ’140 Patent Issue Date |
| 2015-03-10 | ’797 Patent Issue Date |
| 2016-12-27 | ’769 Patent Issue Date |
| 2017-07-11 | ’750 Patent Issue Date |
| 2019-08-10 | Alleged infringing shipment of "COMPUTER PARTS" to U.S. subsidiary |
| 2023-12-22 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,703,750 - Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions
The Invention Explained
- Problem Addressed: Traditional computer interconnections, like the peripheral component interconnect (PCI) bus, relied on parallel data transmission using a large number of pins, which was power-inefficient, generated electrical noise, and was not well-suited for modular or cabled computer designs (Compl. ¶36).
- The Patented Solution: The invention describes a method for improving computer communication by using an integrated single-chip CPU and graphics controller that connects directly to various high-speed serial channels. These channels, described as Low Voltage Differential Signal (LVDS) channels, use pairs of unidirectional lanes to transmit data for different protocols (e.g., USB, digital video) in opposite directions, replacing the bulky parallel buses (’797 Patent, col. 5:32-67). This architecture enables faster, more power-efficient, and scalable connections.
- Technical Importance: This technological approach of serializing data over LVDS channels became a foundational principle for modern high-speed interconnect standards like PCI Express and USB 3.x, enabling significant increases in data transfer speeds within computer systems (Compl. ¶1, ¶46).
Key Claims at a Glance
- The complaint asserts at least claim 50, which depends from independent method claim 19 (Compl. ¶100).
- Essential elements of independent claim 19 include:
- A method of improving external peripheral data communication in a computer;
- obtaining an integrated central processing unit (CPU) and graphics controller as a single chip;
- connecting a unidirectional signal channel directly to the integrated CPU and graphics controller to output digital video data;
- providing a connector for external peripheral data communication;
- providing a first Low Voltage Differential Signal (LVDS) channel to convey Universal Serial Bus (USB) protocol data through the connector;
- wherein the first LVDS channel comprises two unidirectional, serial bit channels that transmit data in opposite directions.
- The complaint reserves the right to assert additional claims (Compl. ¶102).
U.S. Patent No. 8,977,797 - Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel
The Invention Explained
- Problem Addressed: The patent’s background section identifies the limitations of prior art interfaces that couple two independent computer buses, noting that reliance on the PCI protocol makes such interfaces not "cable friendly" and require a very large number of signal channels and connector pins (’797 Patent, col. 3:9-52).
- The Patented Solution: The invention proposes a method to improve data throughput by using an LVDS channel to serially transmit data from a PCI bus transaction. The method involves mounting an integrated CPU and interface controller on a motherboard and connecting it to an LVDS channel that uses multiple pairs of differential signal lines. This architecture allows the interface controller to be configured for different numbers of signal lines, making the connection scalable to handle increasing data demands (’797 Patent, Abstract, col. 5:32-47).
- Technical Importance: The claimed method provides a scalable, high-performance architecture that reduces pin counts and power consumption, embodying the principles later adopted by the PCI Express standard (Compl. ¶46, ¶49).
Key Claims at a Glance
- The complaint asserts at least independent method claim 36 (Compl. ¶114).
- Essential elements of independent claim 36 include:
- A method of improving data throughput on a motherboard;
- mounting an integrated central processing unit (CPU) and an interface controller as a single chip on the motherboard;
- connecting a Low Voltage Differential Signal (LVDS) channel directly to the interface controller, which uses two unidirectional, serial channels;
- increasing data throughput by providing each channel with multiple differential signal line pairs;
- configuring the interface controller to adapt to different numbers of differential signal line pairs to convey encoded PCI bus transaction data in serial form;
- coupling the integrated CPU and interface device to a peripheral device via the LVDS channel.
- The complaint reserves the right to assert additional claims (Compl. ¶116).
U.S. Patent No. 9,529,769 - Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction In Opposite Directions
- Technology Synopsis: This patent claims a method of improving external peripheral data communication by using an integrated CPU/graphics chip that connects to LVDS channels. These channels are used to convey both USB protocol data and digital video data through a common connector.
- Asserted Claims: At least independent claim 19 (Compl. ¶126).
- Accused Features: The accused products’ use of integrated processors with direct connections to USB 3.x ports and digital video outputs (e.g., DisplayPort, DVI, HDMI) is alleged to practice the claimed manufacturing method (Compl. ¶126).
U.S. Reissue Patent No. RE45,140 - Data Security Method and Device for Computer Modules
- Technology Synopsis: This patent claims a method for improving a computer’s performance by manufacturing it with an integrated CPU and graphics controller. The integrated unit connects directly to a first LVDS channel for peripheral communication (e.g., USB, Thunderbolt) and a second differential signal channel for outputting digital video data.
- Asserted Claims: At least independent claim 35 (Compl. ¶137).
- Accused Features: The manufacturing of accused products with integrated processors connected to PCIe, DMI, USB 3.x, and digital video channels is alleged to infringe (Compl. ¶137).
U.S. Reissue Patent No. RE44,654 - Data Security Method and Device for Computer Modules
- Technology Synopsis: This patent claims a method of increasing data communication speed by connecting a CPU directly to a peripheral bridge on a circuit board. This connection is facilitated by an LVDS channel that transmits data in opposite directions. The method also includes providing a second LVDS channel to connect the computer to a console for protocols like USB.
- Asserted Claims: At least independent claim 23 (Compl. ¶149).
- Accused Features: The accused products allegedly practice the claimed method by connecting an Intel CPU to an Intel PCH (peripheral bridge) via a DMI connection (the alleged LVDS channel) and by providing USB 3.x and Thunderbolt ports for console connectivity (Compl. ¶149).
III. The Accused Instrumentality
Product Identification
- The complaint identifies the "Accused Advantech Products," which include product categories such as servers, networking hardware, and application-specific computers (Compl. ¶62-64). The infringement allegations focus on two exemplary products: the AIMB-585 motherboard, categorized as an "Accused Server," and the MIO-2360, an embedded single-board computer categorized as an "Accused PC" (Compl. ¶67, ¶79).
Functionality and Market Context
- The accused products are computer motherboards and single-board computers that integrate a central processing unit (CPU) with a graphics subsystem and interface controllers onto a single chip, such as the Intel® Core™ and Celeron® processors (Compl. ¶70, ¶81).
- Their core functionality relevant to the dispute involves the use of modern serial interconnect standards, including PCIe, Direct Media Interface (DMI), SATA, USB 3.x, HDMI, and DisplayPort, to manage data flow between the processor, chipsets, memory, storage, and external peripherals (Compl. ¶72-76, ¶82-85). The complaint includes a block diagram for the AIMB-585 motherboard that illustrates the direct connections from the processor to various high-speed data channels (Compl. p. 23).
- Plaintiff alleges Advantech is a "world's leading industrial computer factory" and that the United States is its second-largest market, generating substantial revenue from the sale of the accused product categories (Compl. ¶10, ¶57, ¶59).
IV. Analysis of Infringement Allegations
U.S. Patent No. 9,703,750 Infringement Allegations
| Claim Element (from Independent Claim 19) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a method of improving external peripheral data communication in a computer | The method is allegedly performed when Advantech or another party manufactures the accused products, such as the AIMB-585 and MIO-2360. | ¶100, ¶105 | col. 48:48-50 |
| obtaining an integrated central processing unit (CPU) and graphics controller as a single chip | The accused products utilize single-chip processors (e.g., Intel 6th Gen Core, Intel Celeron) that integrate both CPU and graphics controller functions. | ¶100(b), ¶105(g) | col. 48:51-53 |
| connecting a unidirectional signal channel directly to the integrated CPU and graphics controller to output digital video data | The processors in the accused products directly connect to and output video signals via DDI channels, such as DisplayPort, HDMI, and DVI ports. A block diagram of the MIO-2360 shows a direct connection from the processor SoC to transmitters for VGA and HDMI (Compl. p. 32). | ¶100(c), ¶105(h) | col. 48:54-57 |
| providing a connector for external peripheral data communication | The motherboards and single-board computers provide a variety of external ports, including USB 3.x, HDMI, and DisplayPort connectors. | ¶100(d), ¶105(i) | col. 48:58-59 |
| providing a first Low Voltage Differential Signal (LVDS) channel to convey Universal Serial Bus (USB) protocol data through the connector, the first LVDS channel comprising two unidirectional, serial bit channels that transmit data in opposite directions | The accused products provide USB 3.x ports, which allegedly operate as LVDS channels using two unidirectional, differential signal pairs to transmit data in opposite directions. | ¶100(e), ¶105(a) | col. 48:60-66 |
- Identified Points of Contention:
- Scope Questions: A primary question will be whether industry-standard interfaces like USB 3.x and digital video interfaces (DVI, HDMI, DisplayPort) fall within the scope of the terms "Low Voltage Differential Signal (LVDS) channel" and "unidirectional signal channel" as used in the patent.
- Technical Questions: The analysis may focus on whether the accused products' implementation of the USB 3.x protocol, which includes both SuperSpeed and legacy USB 2.0 signaling, constitutes a "first LVDS channel" that operates in the specific manner required by the claim.
U.S. Patent No. 8,977,797 Infringement Allegations
| Claim Element (from Independent Claim 36) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a method of improving data throughput on a motherboard | The method is allegedly performed during the manufacturing of the accused motherboards and single-board computers. | ¶114(a), ¶117(a) | col. 42:25-26 |
| mounting an integrated central processing unit (CPU) and an interface controller as a single chip on the motherboard | The accused products use Intel processors that allegedly integrate the CPU and interface controllers (for DMI/PCIe channels) onto a single chip. | ¶114(b), ¶117(b) | col. 42:27-30 |
| connecting a Low Voltage Differential Signal (LVDS) channel directly to the interface controller, which LVDS channel uses two unidirectional, serial channels to transmit data in opposite directions | The PCIe and DMI interfaces in the accused products are alleged to be LVDS channels with bidirectional data transmission capabilities that connect directly to the processor's integrated interface controller. A block diagram for the AIMB-585 highlights the DMI and PCIe channels extending from the processor (Compl. p. 26). | ¶114(c), ¶117(c) | col. 42:31-36 |
| increasing data throughput in the serial channels by providing each channel with multiple differential signal line pairs | The PCIe and DMI channels in the accused products allegedly utilize multiple pairs of differential signal lanes to increase data throughput. | ¶114(d), ¶117(d) | col. 42:37-40 |
| configuring the interface controller to adapt to different numbers of differential signal line pairs to convey encoded address and data bits of a PCI bus transaction in serial form | The integrated interface controllers are allegedly configured to convey PCIe data, which is based on the PCI bus transaction model, through scalable PCIe channels having multiple signal line pairs. | ¶114(e), ¶117(e) | col. 42:41-45 |
| coupling the integrated CPU and the interface device to a peripheral device such as a mass storage device, which is attached to the motherboard through the LVDS channel | The accused products are allegedly configured to couple the CPU to peripheral devices, such as a mass storage drive (HDD/SSD), via PCIe or other channels identified as LVDS channels. | ¶114(f), ¶117(f) | col. 42:46-50 |
- Identified Points of Contention:
- Scope Questions: As with the ’750 patent, a central issue will be whether standard interconnects like PCIe and DMI are properly characterized as a "Low Voltage Differential Signal (LVDS) channel."
- Technical Questions: The infringement analysis for this patent will likely focus on the "single chip" limitation. The accused products use a CPU connected to a separate Platform Controller Hub (PCH) chipset. A key question will be whether the "interface controller" required by the claim is located on the CPU die itself or whether its primary functions reside within the separate PCH, potentially placing it outside the claim scope.
V. Key Claim Terms for Construction
The Term: "Low Voltage Differential Signal (LVDS) channel"
Context and Importance: This term is foundational to all asserted patents. Infringement hinges on whether standard, high-speed serial interfaces like PCIe, DMI, and USB 3.x, which are used in the accused products, fall within the term's scope. Practitioners may focus on this term because its definition will likely determine the outcome for all asserted claims.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification of the ’797 Patent states, "The term LVDS is herein used to generically refer to low voltage differential signals and is not intended to be limited to any particular type of LVDS technology" (’797 Patent, col. 4:1-4). This language may support an interpretation that covers any interface using the underlying principle of LVDS, including standardized ones.
- Evidence for a Narrower Interpretation: The patents extensively describe a proprietary "XPBus" architecture (e.g., ’797 Patent, Figs. 9-15). A defendant may argue that the claims, when read in light of these specific embodiments, should be construed more narrowly to cover only such proprietary interfaces and not later-developed, separately-defined industry standards.
The Term: "interface controller as a single chip" (from ’797 Patent, Claim 36)
Context and Importance: Infringement of claim 36 of the ’797 Patent requires the CPU and "interface controller" to be on a "single chip." The accused products use CPUs that connect to a separate PCH chipset. The dispute will likely concern whether the functionalities of the claimed "interface controller" are integrated onto the CPU die or reside primarily in the separate PCH.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The complaint alleges the Intel processors in the accused products include integrated controllers for driving DMI and PCIe channels (Compl. ¶114(b)). This aligns with modern processor design where some I/O control logic, such as a PCIe root complex, is integrated directly onto the CPU die.
- Evidence for a Narrower Interpretation: The patent's block diagrams, such as Figure 8, depict the "Integrated Host Interface Cntlr. & North Bridge" as a distinct block from the CPU (’797 Patent, Fig. 8). A defendant may argue this shows an intended separation, and that in the accused products, the PCH (a separate chip) performs the primary functions of the claimed "interface controller." The complaint's own visual evidence depicts the processor and chipset as separate blocks connected by DMI (Compl. p. 23).
VI. Other Allegations
- Willful Infringement: Plaintiff alleges willful infringement based on Defendant’s alleged pre-suit knowledge of the patents. The complaint states that on or around April 30, 2013, ACQIS sent a notice letter to Advantech identifying certain patents and accused product categories (Compl. ¶90). The complaint alleges that Advantech did not provide a meaningful response and continued its allegedly infringing activities, thereby acting in reckless disregard of Plaintiff's patent rights (Compl. ¶92-95).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: Can the term “Low Voltage Differential Signal (LVDS) channel,” which is described in the patents as a novel interface, be construed to cover ubiquitous, standardized interconnects like PCIe, DMI, and USB 3.x that were developed and adopted by the industry? The answer will likely dictate the outcome of the infringement analysis for all five asserted patents.
- A key technical question will be one of architectural mapping: For the claims requiring an "integrated CPU and an interface controller as a single chip," does the functionality of the claimed "interface controller" reside on the CPU die of the accused products, or is it primarily performed by the separate PCH chipset? This analysis will require a detailed examination of the specific processor and chipset architectures employed.
- A central evidentiary question will concern willfulness: Did the alleged 2013 notice letter provide Defendant with sufficient knowledge of its potential infringement to support a finding of willful misconduct, and what actions, if any, did Defendant take in response to that notice?