DCT
6:23-cv-00884
Acqis LLC v. Cisco Systems, Inc.
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Acqis LLC (Texas)
- Defendant: Cisco Systems, Inc. (Delaware)
- Plaintiff’s Counsel: Scott Douglass & McConnico LLP; Dorsey & Whitney LLP
- Case Identification: 6:23-cv-00884, W.D. Tex., 12/22/2023
- Venue Allegations: Plaintiff alleges venue is proper because Defendant maintains an established place of business in the district, has previously litigated patent cases in the district without contesting venue, and has imported accused products to an address within the district. The complaint also notes that the patents-in-suit have been previously asserted in this court, suggesting judicial efficiency supports venue.
- Core Dispute: Plaintiff alleges that Defendant’s computer servers infringe patents related to methods of improving data communication performance by using low voltage differential signal (LVDS) channels for high-speed serial data transmission.
- Technical Context: The technology concerns computer architecture for high-speed data interconnects, replacing older parallel bus technologies (like PCI) with more efficient serial transmission methods that have become foundational for modern standards such as PCI Express (PCIe) and USB 3.x.
- Key Procedural History: The patents-in-suit have been asserted in prior litigation in the same district against other defendants, including cases with scheduled trials. The ’654 patent is a reissue of U.S. Patent No. 6,643,777, which issued in 2003.
Case Timeline
| Date | Event |
|---|---|
| 1999-05-14 | Earliest Priority Date for ’797 and ’654 Patents |
| 2003-11-04 | Issue Date of U.S. Patent No. 6,643,777 (original ’654) |
| 2013-12-17 | Issue Date of ’654 Reissue Patent |
| 2015-03-10 | Issue Date of ’797 Patent |
| 2018-03-19 | Launch Date for exemplary Cisco UCS C480 M5 Rack Server |
| 2023-12-22 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 8,977,797 - "Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel," issued March 10, 2015
The Invention Explained
- Problem Addressed: Traditional computer interconnections, such as the Peripheral Component Interconnect (PCI) bus, relied on parallel data transmission using a large number of signal channels and connector pins (Compl. ¶26). This architecture was not "cable friendly" and made it difficult to employ more power-efficient, lower-noise technologies like Low Voltage Differential Signaling (LVDS) (’797 Patent, col. 3:40-59).
- The Patented Solution: The invention describes methods and systems for bridging two computer interface buses (e.g., PCI buses) using a non-PCI, serial interface channel that utilizes LVDS (’797 Patent, col. 5:35-50). By encoding parallel PCI bus signals into serial bit streams for transmission over the LVDS channel, the system reduces the required number of conductive lines and connector pins, enabling a more compact, power-efficient, and high-performance interconnect (’797 Patent, col. 5:41-61). Figure 8B of the patent illustrates a highly integrated embodiment where the CPU, core logic, and interface controller are combined on a single chip (’797 Patent, Fig. 8B).
- Technical Importance: This architectural approach of serializing parallel bus data for transmission over high-speed differential signal channels was a key step in moving the industry beyond the physical and electrical limitations of parallel buses, paving the way for modern standards like PCIe and USB (Compl. ¶1, ¶31).
Key Claims at a Glance
- The complaint asserts independent method claim 36 (Compl. ¶63).
- The essential elements of claim 36 are:
- A method of improving data throughput on a motherboard, comprising:
- mounting an integrated Central Processing Unit (CPU) and interface controller as a single chip on the motherboard;
- connecting a Low Voltage Differential Signal (LVDS) channel directly to the interface controller integrated with the CPU, the LVDS channel using two unidirectional, serial channels to transmit data in opposite directions;
- increasing data throughput of the serial channels by providing each channel with multiple differential signal line pairs;
- configuring the interface controller to adapt to different numbers of differential signal line pairs for conveying encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form; and
- coupling the integrated CPU and interface device to a peripheral device attached to the motherboard through the LVDS channel with the adapted number of differential signal line pairs.
- The complaint reserves the right to assert additional claims (Compl. ¶64).
U.S. Reissue Patent No. RE44,654 - "Data Security Method and Device for Computer Modules," issued December 17, 2013
The Invention Explained
- Problem Addressed: As with the ’797 patent, the technology addresses the limitations of traditional parallel bus interconnections between a core computing module and peripheral components, which were power-intensive and required high pin counts, hindering scalability and the use of LVDS channels (Compl. ¶26).
- The Patented Solution: The asserted claims describe a manufacturing method for increasing data communication speed by directly connecting a CPU to a peripheral bridge on a circuit board and then connecting LVDS channels to that bridge (’654 Patent, claim 23). The method includes providing one LVDS channel for on-board communication and a second LVDS channel via an external connector to a console, with the second channel specifically enabled for transmitting USB protocol data (’654 Patent, claim 23).
- Technical Importance: The invention provides a method for implementing high-speed serial interconnects for both internal components and external peripherals using a common architectural approach, facilitating the adoption of standards like USB for external data communication (Compl. ¶31).
Key Claims at a Glance
- The complaint asserts independent method claim 23 (Compl. ¶71).
- The essential elements of claim 23 are:
- A method of increasing data communication speed of a computer, comprising the steps of:
- connecting a Central Processing Unit (CPU) directly to a peripheral bridge on a printed circuit board;
- connecting a Low Voltage Differential Signal (LVDS) channel directly to the peripheral bridge, the LVDS channel comprising two unidirectional, serial channels to transmit data in opposite directions;
- providing a connector to connect the computer to a console;
- providing a second LVDS channel through the connector to the console, the second LVDS channel comprising two unidirectional, serial channels to transmit data in opposite directions; and
- enabling the transmission of USB protocol data through the second LVDS channel.
- The complaint reserves the right to assert additional claims (Compl. ¶73).
III. The Accused Instrumentality
Product Identification
The accused products include various computer servers sold under the Cisco Unified Computing System (UCS) brand, including B-Series Blade Servers, C-Series Rack Mount Servers, and E-Series Servers (Compl. ¶39). The complaint uses the Cisco UCS C480 M5 Rack Server as a representative example for its infringement analysis (Compl. ¶46-47).
Functionality and Market Context
- The accused servers utilize Intel® Xeon® Scalable processors, which integrate the CPU and an I/O controller (IIO) onto a single silicon die (Compl. ¶48, ¶63(b)).
- These processors connect directly to various high-speed serial interconnects that the complaint characterizes as LVDS channels, including PCI Express (PCIe) slots, an Intel DMI interface to the chipset, and USB 3.x ports (Compl. ¶49-51). An Intel technical diagram illustrates the direct connection from the CPU to 48 lanes of PCIe as well as a DMI link to a chipset (Compl. p. 13).
- The complaint alleges that sales of these servers generate millions of dollars in revenue and that U.S. revenue comprises over half of Defendant's worldwide revenue, positioning the products as commercially significant (Compl. ¶36-37).
IV. Analysis of Infringement Allegations
’797 Patent Infringement Allegations
| Claim Element (from Independent Claim 36) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A method of improving data throughput on a motherboard... | The manufacturing of the Cisco UCS C480 M5 Rack Server, which contains a motherboard, is alleged to be a performance-improving method. | ¶63(a) | col. 39:27-29 |
| mounting an integrated Central Processing Unit (CPU) and interface controller as a single chip on the motherboard | The Intel Xeon processor used in the server is alleged to integrate the CPU and interface controllers (for driving PCIe channels) onto a single chip, which is mounted on the server's motherboard. | ¶63(b) | col. 12:2-9 |
| connecting a Low Voltage Differential Signal (LVDS) channel directly to the interface controller integrated with the CPU, the LVDS channel using two unidirectional... | The server's PCIe channels and DMI interface are alleged to be LVDS channels connected directly to the processor's integrated interface controller, using pairs of lanes for bidirectional data transmission. | ¶63(c) | col. 22:13-24 |
| increasing data throughput of the serial channels by providing each channel with multiple differential signal line pairs | The PCIe and DMI channels are alleged to use multiple pairs of differential signal lanes to increase data throughput. | ¶63(d) | col. 42:29-37 |
| configuring the interface controller to adapt to different numbers of differential signal line pairs for conveying encoded address and data bits of a... PCI bus transaction... | The integrated interface controllers are alleged to be configured to convey PCIe data signals through PCIe channels, which can adapt to different numbers of signal line pairs (i.e., different lane widths). A diagram shows the server's rear panel with multiple PCIe slots (Compl. p. 12, Fig. 2). | ¶63(e) | col. 42:38-46 |
| coupling the integrated CPU and interface device to a peripheral device attached to the motherboard through the LVDS channel... | The integrated CPU and interface are coupled to peripheral devices like a storage interface controller or graphics processor through a PCIe channel, which is alleged to be an LVDS channel. | ¶63(f) | col. 42:47-52 |
Identified Points of Contention
- Scope Questions: A central question may be whether the term "LVDS channel", as used in a patent with a 1999 priority date, can be construed to read on the distinct, standardized protocols of PCIe and DMI as alleged. The patent includes a broad generic definition of LVDS, which may support the plaintiff's position (’797 Patent, col. 4:1-5).
- Technical Questions: The analysis may focus on whether the accused Intel processor's integrated I/O controller (IIO) is structurally and functionally equivalent to the "interface controller" disclosed in the patent, which is often depicted as a separate Host Interface Controller (HIC). Another question is what evidence supports the allegation that the controller actively "adapts" to different numbers of signal line pairs in the manner required by the claim.
’654 Patent Infringement Allegations
| Claim Element (from Independent Claim 23) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A method of increasing data communication speed of a computer... | Manufacturing the Cisco UCS C480 M5 Rack Server is alleged to be a method of increasing data communication speed. | ¶71(a) | col. 23:25-27 |
| connecting a Central Processing Unit (CPU) directly to a peripheral bridge on a printed circuit board | The server's Intel core CPU is alleged to be connected directly to the Intel Platform Controller Hub (PCH), which is identified as the claimed "peripheral bridge," via a DMI connection. | ¶71(b) | col. 23:28-30 |
| connecting a Low Voltage Differential Signal (LVDS) channel directly to the peripheral bridge, the LVDS channel comprising two unidirectional, serial channels... | The DMI channel connecting the CPU and PCH is alleged to be the claimed LVDS channel, using two unidirectional serial channels. | ¶71(c) | col. 23:31-35 |
| providing a connector to connect the computer to a console | The server is alleged to have various connector ports, such as USB 3.x, that connect the computer to a console. | ¶71(d) | col. 23:36-37 |
| providing a second LVDS channel through the connector to the console, the second LVDS channel comprising two unidirectional, serial channels... | The server's USB 3.x ports and channels are alleged to constitute the claimed "second LVDS channel." | ¶71(e) | col. 23:38-42 |
| enabling the transmission of USB protocol data through the second LVDS channel | The server is alleged to enable the transmission of USB protocol data via its USB 3.x port and channel. A rear panel diagram shows the presence of three USB 3.0 ports (Compl. p. 12, Fig. 2, item 8). | ¶71(f) | col. 23:43-45 |
Identified Points of Contention
- Scope Questions: The dispute may turn on whether the Intel PCH chipset, a complex, multi-function component, meets the definition of a "peripheral bridge" as understood in the context of the patent. Additionally, as with the ’797 patent, the case raises the question of whether a modern USB 3.x interface falls within the scope of the term "LVDS channel."
- Technical Questions: A key question is whether connecting a CPU to a PCH via a DMI link constitutes a "direct" connection to a "peripheral bridge" in the manner claimed by the patent.
V. Key Claim Terms for Construction
The Term: "interface controller integrated with the CPU" (’797 Patent, claim 36)
- Context and Importance: Plaintiff’s infringement theory for the ’797 patent relies on mapping this term to the integrated I/O (IIO) controller on the die of the accused Intel Xeon processors. The construction of "integrated" will be critical.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent specification explicitly discloses a "single chip fully integrated" embodiment, described as an "Attached Computer Module with Single Chip...: CPU, Cache, Core Logic, Graphics Controller and Interface Controller" (’797 Patent, Fig. 8B, col. 12:2-9). This suggests the inventor contemplated a high degree of on-chip integration.
- Evidence for a Narrower Interpretation: Many embodiments in the patent depict the "Host Interface Controller" as a block distinct from the CPU and North Bridge (e.g., ’797 Patent, Fig. 6, element 619). A party could argue that this separation is the primary teaching and that "integrated" should be limited to the specific combination shown in Figure 8B.
The Term: "peripheral bridge" (’654 Patent, claim 23)
- Context and Importance: The complaint alleges that the Intel PCH chipset in the accused servers is a "peripheral bridge" (Compl. ¶71(b)). Whether this complex, modern chipset falls within the patent's definition of this term is central to the infringement analysis for the ’654 patent.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification of the original patent (U.S. Pat. No. 6,643,777) frequently refers to North and South Bridges, which connect the CPU to various I/O buses. For example, it describes the "North Bridge" as a "PCI bus bridge" and a component that connects the CPU to memory and graphics (e.g., ’777 Patent, col. 4:24-28). This may support a functional definition where any component performing this bridging role qualifies.
- Evidence for a Narrower Interpretation: A party might argue that the term should be limited to the specific North/South Bridge chipsets common in the 1999-era art disclosed in the patent, and that a modern PCH, which consolidates numerous functions, is a distinct and non-equivalent structure.
VI. Other Allegations
- Indirect Infringement: The complaint makes a general allegation that Defendant has induced acts of patent infringement (Compl. ¶11) but does not plead specific supporting facts, such as identifying user manuals or marketing materials that instruct customers to use the accused servers in an infringing manner.
- Willful Infringement: The complaint does not allege specific facts to support a claim of willful infringement, such as pre-suit knowledge of the patents-in-suit.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of technological scope: can the term "LVDS channel," rooted in patents with a 1999 priority date and defined broadly therein, be construed to encompass the distinct, modern, and highly standardized serial interconnect protocols of PCI Express, DMI, and USB 3.x?
- A key question of claim construction will be whether the architectural components of the accused servers map onto the patent claims. Specifically, does the integrated I/O controller on a modern Intel Xeon CPU meet the definition of an "interface controller integrated with the CPU," and does a multi-function Platform Controller Hub (PCH) chipset meet the definition of a "peripheral bridge" as those terms are used in the patent specifications?
- A central evidentiary question will be one of functional performance: what evidence will be presented to demonstrate that the manufacturing and operation of the accused servers meet the specific functional steps of the asserted method claims, such as the interface controller "adapting" to different numbers of signal lines?