DCT

6:24-cv-00248

Acqis LLC v. Adlink Technology Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:24-cv-00248, W.D. Tex., 05/10/2024
  • Venue Allegations: Plaintiff alleges venue is proper because Defendants are not U.S. residents and may be sued in any judicial district. It also cites judicial efficiency, noting that the asserted patents have been and are currently being litigated in other cases before the Western District of Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s computer products, including embedded computers, servers, and motherboards, infringe a portfolio of nine patents related to high-speed serial data transmission technologies that are foundational to standards like PCI Express and USB 3.x.
  • Technical Context: The patents relate to methods for converting parallel data from computer bus architectures (like PCI) into high-speed serial bitstreams for transmission over low voltage differential signal (LVDS) channels, a foundational technology for modern computer input/output interfaces.
  • Key Procedural History: The complaint notes that the ACQIS patent portfolio has been the subject of prior litigation, including a lawsuit against IBM that resulted in a jury verdict. It also identifies several other pending cases in the Western District of Texas against entities such as Quanta Computer and ASUSTeK, suggesting a coordinated, multi-front litigation campaign by ACQIS to enforce this portfolio.

Case Timeline

Date Event
1999-05-14 Earliest Priority Date for all Patents-in-Suit
2012-07-31 U.S. Patent No. 8,234,436 Issues
2013-04-30 Plaintiff alleges sending actual notice letter to Defendant
2013-12-17 U.S. Patent No. RE44,654 Issues
2014-01-07 U.S. Patent No. 8,626,977 Issues
2014-01-28 U.S. Patent No. RE44,739 Issues
2014-06-17 U.S. Patent No. 8,756,359 Issues
2014-09-16 U.S. Patent No. RE45,140 Issues
2015-03-10 U.S. Patent No. 8,977,797 Issues
2016-12-27 U.S. Patent No. 9,529,768 Issues
2017-07-11 U.S. Patent No. 9,703,750 Issues
2018-01-01 Defendant's accused products allegedly sold since at least this year
2024-05-10 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,529,768

  • Patent Identification: 9,529,768, “Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions,” issued December 27, 2016.

The Invention Explained

  • Problem Addressed: The patent’s background describes the limitations of traditional computer interconnections, such as the Peripheral Component Interconnect (PCI) bus, which used a large number of parallel signal channels. This approach made it difficult to employ more "cable friendly," lower-power, and less noisy technologies like Low Voltage Differential Signal (LVDS) channels (Compl. ¶38).
  • The Patented Solution: The invention proposes a computer system architecture where an interface controller, integrated with the Central Processing Unit (CPU) in a single chip, is directly connected to an LVDS channel. This channel converts parallel PCI bus transaction data (address and data bits) into a serial bitstream for high-speed transmission using pairs of unidirectional differential signal paths operating in opposite directions (’977 Patent, Abstract; col. 4:8-41).
  • Technical Importance: This architecture provided a scalable, power-efficient, and high-performance interconnection system using connectors with low pin counts, which became a foundational concept for modern serial bus standards like PCI Express (Compl. ¶38, 52).

Key Claims at a Glance

  • The complaint asserts at least independent claim 13 (Compl. ¶104).
  • Essential elements of Claim 13 include:
    • A computer comprising an integrated central processing unit (CPU) and interface controller in a single chip.
    • A first LVDS channel directly extending from the interface controller to convey address and data bits of a PCI bus transaction in a serial bit stream.
    • The first LVDS channel comprises first and second unidirectional, multiple, differential signal pairs to convey data in opposite directions.
    • System memory directly coupled to the integrated CPU and interface controller.
  • The complaint reserves the right to assert additional claims (Compl. ¶106).

U.S. Patent No. 9,703,750

  • Patent Identification: 9,703,750, “Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions,” issued July 11, 2017.

The Invention Explained

  • Problem Addressed: The technology addresses the need for improved external peripheral data communication for computers, moving away from cumbersome parallel bus technologies toward more efficient serial communication methods (Compl. ¶38).
  • The Patented Solution: The patent describes a method for manufacturing a computer where an integrated CPU and graphics controller is connected to various I/O channels. Specifically, it discloses providing a connector for external peripherals and using an LVDS channel to convey USB protocol data through that connector via two unidirectional serial bit channels (’977 Patent, col. 4:8-41, col. 6:4-16). This solution facilitates high-speed data transfer to external devices using a low-pin-count serial interface.
  • Technical Importance: This method established a framework for integrating high-speed serial peripheral connections like USB 3.x directly into the core CPU architecture, improving performance and simplifying computer design (Compl. ¶51, 56).

Key Claims at a Glance

  • The complaint asserts at least independent claim 50 (Compl. ¶115).
  • Essential elements of Claim 50 (a method claim) include:
    • Obtaining an integrated CPU and graphics controller as a single chip.
    • Connecting a first unidirectional, differential signal pair channel directly to the integrated CPU and graphics controller.
    • Providing a connector for external peripheral data communication.
    • Providing an LVDS channel to convey USB protocol data through the connector using two unidirectional serial bit channels that transmit data in opposite directions.
  • The complaint reserves the right to assert additional claims (Compl. ¶117).

Additional Patents-in-Suit

  • Patent Identification: U.S. Patent No. 8,756,359, “Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits,” issued June 17, 2014.

  • Technology Synopsis: This patent claims a computer system with a CPU directly connected to a first LVDS channel composed of opposing unidirectional signal pairs. It also claims a second LVDS channel that can couple to a console via a USB 3.x port to convey USB protocol data (Compl. ¶125).

  • Asserted Claims: At least independent claim 6 (Compl. ¶125).

  • Accused Features: The accused products allegedly implement this technology through their use of 6th Generation Intel Core processors with direct connections to PCIe and USB 3.x channels (Compl. ¶125(d)-(e)).

  • Patent Identification: U.S. Patent No. 8,626,977, “Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits,” issued January 7, 2014.

  • Technology Synopsis: This patent claims a computer with an integrated CPU and graphics subsystem in a single chip. The system includes an LVDS channel extending from the CPU for transmitting PCI bus transaction data in a serial stream, as well as serial bit channels coupled to a USB-3.x port for conveying USB protocol data packets (Compl. ¶135).

  • Asserted Claims: At least independent claim 1 (Compl. ¶135).

  • Accused Features: The complaint alleges that the accused products' Intel processors, with their integrated graphics and direct connections to PCIe and USB 3.x channels, embody the claimed system (Compl. ¶135(d)-(f)).

  • Patent Identification: U.S. Reissue Patent No. RE44,739, “Data Security Method and Device for Computer Modules,” issued January 28, 2014.

  • Technology Synopsis: This patent claims a computer system with an integrated CPU and graphics controller directly coupled to a first differential signal channel for digital video. A second LVDS channel with at least two pairs of unidirectional lanes is used to transmit data, including USB 3.x data, in opposite directions upon coupling to a console (Compl. ¶145).

  • Asserted Claims: At least independent claim 18 (Compl. ¶145).

  • Accused Features: The accused products' Intel processors allegedly feature direct coupling to video (eDP/DDI) and USB 3.x channels that perform the claimed functions (Compl. ¶145(b)-(e)).

  • Patent Identification: U.S. Patent No. 8,977,797, “Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel,” issued March 10, 2015.

  • Technology Synopsis: This patent describes a method of improving data throughput on a motherboard. The method involves mounting an integrated CPU and interface controller, connecting an LVDS channel to it, and configuring the controller to adapt to different numbers of differential signal line pairs to convey PCI bus transaction data (Compl. ¶156).

  • Asserted Claims: At least independent claim 36 (Compl. ¶156).

  • Accused Features: The complaint alleges that the manufacturing process of the accused products, which use Intel processors with configurable PCIe and DMI channels, necessarily practices the claimed method (Compl. ¶156(b)-(f)).

  • Patent Identification: U.S. Reissue Patent No. RE45,140, “Data Security Method and Device for Computer Modules,” issued September 16, 2014.

  • Technology Synopsis: This patent claims a method of improving computer performance by obtaining an integrated CPU and graphics controller and connecting LVDS channels to it. One LVDS channel is for data transmission in opposite directions, and a second is for outputting digital video data, while a connector is provided for external peripherals like USB 3.x (Compl. ¶167).

  • Asserted Claims: At least independent claim 35 (Compl. ¶167).

  • Accused Features: The manufacturing of the accused products, which use Intel processors with direct connections to PCIe, DMI, DDI, eDP, and USB 3.x ports, is alleged to infringe (Compl. ¶167(b)-(f)).

  • Patent Identification: U.S. Reissue Patent No. RE44,654, “Data Security Method and Device for Computer Modules,” issued December 17, 2013.

  • Technology Synopsis: This patent claims a method of increasing data communication speed by directly connecting a CPU to a peripheral bridge (PCH). An LVDS channel is connected to the PCH for bidirectional data transmission, and a second LVDS channel connects to a console for transmitting USB protocol data (Compl. ¶178).

  • Asserted Claims: At least independent claim 23 (Compl. ¶178).

  • Accused Features: The complaint alleges the accused products, with their Intel CPU directly connected to a PCH via a DMI link and their support for USB 3.x, are manufactured using the claimed method (Compl. ¶178(b)-(f)).

  • Patent Identification: U.S. Patent No. 8,234,436, “Computer System Including Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits,” issued July 31, 2012.

  • Technology Synopsis: This patent claims a computer with an integrated CPU and peripheral controller. The system features a first LVDS channel for bidirectional data (including PCI transaction data) and a second LVDS channel for digital video data, both directly coupled to the integrated CPU (Compl. ¶188).

  • Asserted Claims: At least independent claim 13 (Compl. ¶188).

  • Accused Features: The accused products' use of 6th Gen Intel Core processors with directly coupled PCIe, DMI, eDP, and DDI channels is alleged to meet the claim elements (Compl. ¶188(b)-(f)).

III. The Accused Instrumentality

  • Product Identification: The complaint identifies the "Accused Adlink Products" as a range of computer products including desktops, servers, motherboards, computer-on-modules, and embedded PCs (Compl. ¶63, ¶66). The complaint uses the ADLINK MXC-6400 Series embedded computer as a representative example (Compl. ¶72).
  • Functionality and Market Context: The accused products are alleged to be computer systems that utilize 6th Generation Intel® Core™ processors (codename "Skylake") (Compl. ¶74-75). These processors are described as integrating a CPU, a graphics subsystem, and an interface controller onto a single chip (Compl. ¶76, 104(b)). The complaint alleges these products incorporate various high-speed serial interfaces, such as PCI Express (PCIe), USB 3.x, and DisplayPort, which allegedly operate using LVDS channels to transmit data as serial bit streams in opposite directions (Compl. ¶78-80). A block diagram from an Intel datasheet is provided to illustrate the processor architecture, showing direct connections from the CPU/Processor to PCIe, DDI (configurable as DisplayPort), and USB 3.x channels (Compl. p. 22, Figure 1-1).

IV. Analysis of Infringement Allegations

9,529,768 Infringement Allegations

Claim Element (from Independent Claim 13) Alleged Infringing Functionality Complaint Citation Patent Citation
a computer, comprising: The MXC-6400 Series is a computer. ¶104(a) col. 4:8-10
an integrated central processing unit (CPU) and interface controller in a single chip; The MXC-6400 Series uses 6th Generation Intel® Core™ processors, which are alleged to include interface controllers and the CPU integrated as a single chip. ¶104(b) col. 8:1-4
a first low voltage differential signal (LVDS) channel directly extending from the interface controller to convey address and data bits of a PCI bus transaction in a serial bit stream, The Intel processors allegedly include PCIe channels that are LVDS channels directly extending from the integrated interface controller. These channels are alleged to convey address and data bits of PCI bus transactions. ¶104(c) col. 4:21-26
wherein the first LVDS channel comprises first unidirectional, multiple, differential signal pairs to convey data in a first direction and second unidirectional, multiple, differential signal pairs to convey data in a second, opposite direction; The PCIe channels allegedly comprise unidirectional, differential signal pairs to convey data in opposite directions. ¶104(c) col. 3:45-50
and system memory directly coupled to the integrated CPU and interface controller. The processors in the MXC-6400 Series are allegedly directly coupled to DDR4 system memory. ¶104(d) col. 4:32-35

9,703,750 Infringement Allegations

Claim Element (from Independent Claim 50) Alleged Infringing Functionality Complaint Citation Patent Citation
A method of improving external peripheral data communication of a computer, comprising: obtaining an integrated central processing unit (CPU) and graphics controller as a single chip; The MXC-6400 Series is manufactured using 6th Generation Intel® Core™ processors, which are alleged to be an integrated CPU and graphics controller in a single chip. ¶115(b) col. 3:20-22
connecting a first unidirectional, differential signal pair channel directly to the integrated CPU and graphics controller; During manufacturing, PCIe channels are allegedly connected directly to the integrated CPU, extending from the interface controller. ¶115(c) col. 6:4-16
providing a connector for external peripheral data communication; and The MXC-6400 Series is manufactured with connectors for external peripherals, such as a USB 3.x port. ¶115(d) col. 5:2-4
providing a low voltage differential signal (LVDS) channel to convey Universal Serial Bus (USB) protocol data through the connector, the LVDS channel using two unidirectional, serial bit channels that transmit data in opposite directions. The MXC-6400 Series is manufactured with a USB 3.x port that is an LVDS channel alleged to convey USB 3.x data using two unidirectional channels in opposite directions. ¶115(e) col. 6:4-16

Identified Points of Contention

  • Scope Questions: The asserted patents claim priority to 1999, predating the finalization and widespread adoption of the accused PCI Express and USB 3.x standards. A central dispute may be whether the term "PCI bus transaction," as used and defined in the patents, can be construed to read on the Transaction Layer Packet (TLP) structures used by modern PCIe interfaces (Compl. ¶53). Similarly, it raises the question of whether the patented "LVDS channel" is definitionally broad enough to encompass the specific physical layer implementations of modern PCIe and USB 3.x.
  • Technical Questions: The complaint alleges that LVDS channels are "directly extending from the interface controller" integrated in the CPU (Compl. ¶104(c)). However, the complaint's own visual evidence depicts a system architecture where the CPU connects to a Platform Controller Hub (PCH) via a DMI 3.0 link, and the PCH then provides the main I/O interfaces like PCIe and SATA (Compl. p. 22, Figure 1-1). This architecture raises the question of whether the connection from the CPU's integrated controller to the external PCIe or USB channels is "direct" as claimed, or if the PCH acts as an intervening peripheral bridge that would place the accused products outside the scope of such claims.

V. Key Claim Terms for Construction

  • The Term: "directly extending from the interface controller" (and variants like "directly coupled" or "directly connected")

  • Context and Importance: This term is critical because many asserted claims require a direct link between the claimed "interface controller" (allegedly integrated with the CPU) and the LVDS channel. The accused products utilize a modern chipset architecture with a CPU and a separate PCH chip connected by a DMI bus (Compl. p. 22, Figure 1-1). The defense may argue this PCH is an intervening component that breaks any "direct" connection, while the plaintiff may argue the CPU and PCH function as a single integrated system for the purposes of the claims. Practitioners may focus on this term because its construction could be dispositive of infringement for a significant portion of the asserted claims.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification describes the invention in the context of an "attached computer module (ACM)" connecting to a "peripheral console," where the "interface controller" manages the link between them (’977 Patent, col. 4:42-50). This functional description might support an interpretation where "direct" refers to the primary pathway for data leaving the core processing module, regardless of intermediary chip-level hubs like a PCH.
    • Evidence for a Narrower Interpretation: The patent figures, such as Figure 2, depict a "CPU with North Bridge" connected to a "Peripheral Controller" via a PCI bus (’977 Patent, Fig. 2). This architecture, which lacks a PCH-like component, could be used to argue that "direct" implies a point-to-point connection without an intervening bus controller hub as seen in the accused products.

  • The Term: "interface controller"

  • Context and Importance: The claims require this component to perform specific functions, such as conveying "address and data bits of a PCI bus transaction in a serial bit stream" (’768 Patent, cl. 13). Infringement hinges on whether the controllers integrated into the accused Intel processors perform these functions. The complaint alleges that the Intel PCH contains an "Integrated Clock Controller (ICC) that includes PLL circuitry" used to convey PCI and USB transactions (Compl. ¶84). The construction of "interface controller" will determine what specific functionalities must be proven in the accused devices.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification describes the interface controller functionally as managing transactions between two computer buses and encoding/decoding control signals for transmission over the interface channel (’977 Patent, col. 5:5-15). This functional definition could support a finding that any modern chipset component performing these roles infringes.
    • Evidence for a Narrower Interpretation: The detailed description discloses specific components like a "host interface controller (HIC)" and a "peripheral interface controller (PIC)" with detailed block diagrams showing specific logic for handling PCI signals (’977 Patent, Fig. 9-10). These specific embodiments, including elements like "Bus Controller," "Translator," and "FIFO" buffers, may be cited to argue for a narrower construction that the accused general-purpose CPU/PCH controllers do not meet. The complaint includes a diagram of the accused PCH's internal clock system, which may be compared against the patent's diagrams to highlight differences in structure and operation (Compl. p. 32, Figure 25-1).

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement to infringe by asserting that Defendants actively promote the accused products for the U.S. market, provide instructions to end users on how to use them in an infringing manner, and configure the products such that infringement necessarily occurs upon normal operation (Compl. ¶96, 99).
  • Willful Infringement: The willfulness allegation is based on alleged pre-suit knowledge. The complaint asserts that Plaintiff sent Defendants a notice letter regarding the patent portfolio and the alleged infringement on or around April 30, 2013, more than a decade before the complaint was filed (Compl. ¶87, 94). It also alleges further attempts to negotiate in September 2020 and March 2021 (Compl. ¶91).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can the term “PCI bus transaction,” as defined in patents with a 1999 priority date, be construed to cover the packet-based protocols of modern standards like PCI Express, or does this represent a fundamental technological shift that places the accused products outside the claims’ scope?
  • A second key issue will be one of architectural mismatch: can the claim limitation "directly extending from the interface controller" be interpreted to read on the accused products' CPU-PCH architecture, where a Platform Controller Hub acts as an I/O intermediary, or does the presence of the PCH sever the "direct" connection required by the claims?
  • A central evidentiary question will be one of functional proof: what evidence will be required to demonstrate that the accused Intel processors and chipsets perform the specific functions of encoding, serializing, and decoding PCI bus transaction data as detailed in the patent specifications, and does the complaint's reliance on high-level marketing datasheets and block diagrams provide sufficient factual support to survive a motion to dismiss?