DCT
6:24-cv-00249
Acqis LLC v. Giga Byte Technology Co Ltd
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Acqis LLC (Texas)
- Defendant: GIGA-BYTE TECHNOLOGY CO., LTD. (Taiwan)
- Plaintiff’s Counsel: Dorsey & Whitney LLP; Scott Douglass & McConnico LLP
- Case Identification: 6:24-cv-00249, W.D. Tex., 05/10/2024
- Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign corporation not resident in the United States and may therefore be sued in any judicial district.
- Core Dispute: Plaintiff alleges that Defendant’s computer products, exemplified by its BRIX Mini PC Series, infringe four U.S. patents related to high-speed serial data communication technologies, specifically by importing products manufactured abroad using Plaintiff's patented methods.
- Technical Context: The technology at issue involves methods for improving data throughput between computer components by using low-voltage differential signaling (LVDS) to serially transmit data for protocols like PCI, PCIe, and USB.
- Key Procedural History: The complaint notes that the asserted patents have been the subject of prior litigation in the Western District of Texas, including a case against ASUSTeK Computer Inc. that resulted in a jury verdict of infringement and an award of damages to ACQIS. This history may inform the court's and parties' approaches to claim construction and case management.
Case Timeline
| Date | Event |
|---|---|
| 1999-05-14 | Earliest Priority Date for ’797, ’140, and ’654 Patents |
| 2005-03-31 | Earliest Priority Date for ’769 Patent |
| 2013-12-17 | U.S. Patent No. RE44,654 Issued |
| 2014-09-16 | U.S. Patent No. RE45,140 Issued |
| 2015-03-10 | U.S. Patent No. 8,977,797 Issued |
| 2016-12-27 | U.S. Patent No. 9,529,769 Issued |
| 2017-12-22 | Alleged Infringement Period Begins |
| 2024-05-10 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 8,977,797 - Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel
- Issued: March 10, 2015
The Invention Explained
- Problem Addressed: The patent’s background section describes the limitations of traditional parallel bus architectures like the Peripheral Component Interconnect (PCI) bus. These interfaces required a large number of signal channels and connector pins, making them bulky, power-inefficient, and susceptible to noise, which limited their scalability and use in "cable friendly" applications ('797 Patent, col. 3:9-63).
- The Patented Solution: The invention describes a method for bridging computer interface buses using a low-voltage differential signal (LVDS) channel. Instead of transmitting PCI signals in parallel, the method involves encoding PCI control signals into control bits and transmitting these bits, along with address and data bits, serially over the LVDS channel ('797 Patent, col. 5:32-41). This approach reduces the number of required signal lines, allowing for smaller connectors and enabling higher-speed, lower-power communication ('797 Patent, col. 6:42-50).
- Technical Importance: This approach of serializing parallel bus data for transmission over a high-speed differential channel was foundational to the development of modern computer interconnects that replaced older, bulkier parallel buses (Compl. ¶¶1, 31).
Key Claims at a Glance
- The complaint asserts infringement of at least independent claim 36 ('797 Patent, Compl. ¶80).
- The essential elements of method claim 36 include:
- mounting an integrated CPU and interface controller as a single chip on a motherboard;
- connecting an LVDS channel directly to the interface controller, the channel using two unidirectional, serial channels;
- increasing data throughput by providing each channel with multiple differential signal line pairs;
- configuring the interface controller to adapt to different numbers of signal line pairs to convey encoded PCI bus transaction data in serial form; and
- coupling the integrated CPU and interface device to a peripheral device through a PCIe channel.
- The complaint reserves the right to assert additional claims ('797 Patent, Compl. ¶81).
U.S. Patent No. 9,529,769 - Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction In Opposite Directions
- Issued: December 27, 2016
The Invention Explained
- Problem Addressed: The patent addresses the need for improved, high-performance, and low-power interconnections for computer modules, particularly for connecting a core computing module with peripheral consoles ('769 Patent, col. 1:29-47). Traditional parallel PCI interconnections were described as being difficult to implement with more "cable friendly" LVDS channels ('769 Patent, col. 1:40-47).
- The Patented Solution: The invention proposes a method of improving external peripheral data communication by obtaining an integrated CPU and graphics controller on a single chip and connecting various LVDS channels directly to it for different data types ('769 Patent, Abstract). One channel is used for digital video data, while another is configured to convey USB protocol data using two unidirectional serial bit channels transmitting in opposite directions through a connector ('769 Patent, col. 36:5-20).
- Technical Importance: This method describes a way to consolidate multiple I/O functions onto an integrated processor and use standardized, high-speed serial links for communication, a design principle underlying modern System-on-a-Chip (SoC) architectures (Compl. ¶¶31, 39-40).
Key Claims at a Glance
- The complaint asserts infringement of at least independent claim 19 ('769 Patent, Compl. ¶88).
- The essential elements of method claim 19 include:
- obtaining an integrated CPU and graphics controller as a single chip;
- connecting a unidirectional signal channel directly to the integrated CPU to output digital video data;
- providing a connector for external peripheral data communication;
- providing an LVDS channel to convey USB protocol data through the connector using two unidirectional, serial bit channels; and
- providing a second LVDS channel to convey digital video data through the connector.
- The complaint reserves the right to assert additional claims ('769 Patent, Compl. ¶90).
U.S. Patent No. RE45,140 - Data Security Method and Device for Computer Modules
- Issued: September 16, 2014
- Technology Synopsis: This patent, a reissue of U.S. Patent No. 6,643,777, describes a method for improving computer performance by using an integrated CPU and graphics controller connected to various high-speed serial channels. The method involves connecting an LVDS channel for peripheral data and a separate differential signal channel for digital video data, both directly to the integrated CPU.
- Asserted Claims: The complaint asserts at least method claim 35 (Compl. ¶97).
- Accused Features: The complaint alleges that the manufacturing process for the BRIX Mini PC Series infringes by, among other things, using an integrated Intel "Kaby Lake" processor and connecting PCIe, DMI, DDI, and eDP channels directly to it (Compl. ¶97(b-d)).
U.S. Patent No. RE44,654 - Data Security Method and Device for Computer Modules
- Issued: December 17, 2013
- Technology Synopsis: This patent, also a reissue of U.S. Patent No. 6,643,777, discloses a method for increasing data communication speed by directly connecting a CPU to a peripheral bridge (like a PCH) and then connecting an LVDS channel directly to that bridge. The method facilitates the transmission of both general peripheral data and specific protocol data (like USB) through connectors.
- Asserted Claims: The complaint asserts at least method claim 23 (Compl. ¶106).
- Accused Features: The complaint alleges that the manufacturing process infringes by connecting an Intel Core CPU to an Intel Platform Controller Hub (PCH) via a DMI connection and connecting PCIe channels and USB 3.x ports to the PCH (Compl. ¶106(b-f)).
III. The Accused Instrumentality
Product Identification
- The complaint identifies the "Accused Gigabyte Products," using the BRIX Mini PC Series as an illustrative example (Compl. ¶53).
Functionality and Market Context
- The BRIX Mini PC is a compact computer system that utilizes an Intel Core processor (e.g., 8th Generation "Kaby Lake" family) which integrates a CPU, graphics subsystem, and an interface controller on a single chip (Compl. ¶¶61, 63). The complaint alleges these processors connect directly to various high-speed serial LVDS channels, including PCIe, DMI, USB 3.x, and embedded DisplayPort (eDP) (Compl. ¶¶65-67). A block diagram in the complaint shows the "U-Processor" connecting directly to PCIe lanes, USB 3.1 ports, and a DisplayPort interface (Compl. p. 23, Figure 1-2).
- The complaint further alleges that the Platform Controller Hub (PCH) used in the BRIX Mini PC includes an Integrated Clock Controller with Phase-Locked Loop (PLL) circuitry to generate clock frequencies for PCIe and USB channels (Compl. ¶71). A diagram titled "Integrated Clock Controller (ICC) Diagram" is provided to illustrate the use of multiple PLLs within the PCH (Compl. p. 34, Figure 23-1). These channels are used to connect to peripheral devices such as mass storage (SSD) and external ports like USB-C (Compl. ¶¶64, 69).
IV. Analysis of Infringement Allegations
U.S. Patent No. 8,977,797 Infringement Allegations
| Claim Element (from Independent Claim 36) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a method of improving data throughput on a motherboard, comprising: ... mounting an integrated CPU and interface controller as a single chip on the motherboard | The BRIX Mini PC Series contains a motherboard on which an integrated Intel processor (CPU and interface controller) is mounted. | ¶80(a-b) | col. 25:15-24 |
| connecting an LVDS channel directly to an interface controller integrated with the CPU, which LVDS channel uses two unidirectional, serial channels to transmit data in opposite directions | The BRIX Mini PC has PCIe channels and a DMI interface that are alleged to be LVDS channels directly connected to the integrated interface controller. | ¶80(c) | col. 6:29-37 |
| increasing data throughput in the serial channels by providing each channel with multiple differential signal line pairs | The PCIe and DMI channels allegedly have multiple pairs of differential signal lanes. | ¶80(d) | col. 37:59-65 |
| configuring the interface controller to adapt to different numbers of differential signal line pairs to convey encoded address and data bits of a PCI bus transaction in serial form | The interface controllers in the CPU are allegedly configured to convey PCIe data signals through PCIe channels having differential signal line pairs. | ¶80(e) | col. 42:35-42 |
| coupling the integrated CPU and interface device to a peripheral device such as a storage interface controller or a graphics processor, which is attached to the motherboard through a PCIe channel | The integrated CPU is allegedly coupled to a storage interface controller (for an SSD) or a graphics processor via a PCIe channel. | ¶80(f) | col. 25:55-66 |
Identified Points of Contention
- Scope Questions: The infringement theory hinges on whether modern interconnect standards like PCIe and DMI, developed after the patent's priority date, fall within the scope of the term "LVDS channel" as used in the patent. The analysis may question whether the alleged "configuring" step in manufacturing is a distinct, affirmative act or merely an inherent property of the processor being used.
- Technical Questions: A factual question will be whether the manufacturing process, as performed by or for Gigabyte, includes an explicit step of "configuring the interface controller" as required by the claim, or if the controller's adaptability is a pre-existing feature of the Intel chip that requires no specific manufacturing act to enable.
U.S. Patent No. 9,529,769 Infringement Allegations
| Claim Element (from Independent Claim 19) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a method of improving external peripheral data communication in a computer, comprising: ... obtaining an integrated CPU and graphics controller as a single chip | The BRIX Mini PC Series is manufactured using an 8th Generation Intel® Core™ i7 (“Kaby Lake”) Processor, which is an integrated CPU and graphics controller on a single chip. | ¶88(a-b) | col. 12:20-25 |
| connecting a unidirectional signal channel directly to the integrated CPU and graphics controller to output digital video data | The "Kaby Lake" processors allegedly connect directly to eDP and/or DDI channels to output digital video. | ¶88(c) | col. 34:52-56 |
| providing a connector for external peripheral data communication | The BRIX Mini PC Series provides various connectors, including USB-C. | ¶88(d) | col. 2:23-26 |
| providing an LVDS channel to convey USB protocol data through a connector that uses two unidirectional, serial bit channels that transmit data in opposite directions | The BRIX Mini PC has a USB-C connector that allegedly functions as an LVDS channel conveying USB 3.x data. | ¶88(e) | col. 34:39-49 |
| providing a second LVDS channel to convey digital video data through a connector | The BRIX Mini PC has a USB-C port that can allegedly function as a second LVDS channel to convey/output DisplayPort digital video signals. | ¶88(f) | col. 34:52-56 |
Identified Points of Contention
- Scope Questions: The case may turn on whether providing a single multi-function port (USB-C) that can carry both USB data and DisplayPort video meets the claim requirements of "providing an LVDS channel" and "providing a second LVDS channel."
- Technical Questions: A key question is whether the "unidirectional signal channel" for video output is technically distinct from the "second LVDS channel" for video data, or if the complaint alleges the same physical connection (the DisplayPort alternate mode of a USB-C port) satisfies both limitations.
V. Key Claim Terms for Construction
The Term: "LVDS channel" (from '797 Claim 36; '769 Claim 19)
- Context and Importance: This term is central to the dispute because the plaintiff’s infringement theory requires modern, standardized interconnects like PCIe, DMI, and USB 3.x to be classified as "LVDS channels." Practitioners may focus on this term because its construction will determine whether technology developed years after the patent's priority date is covered by the claims.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent specifications use the term generically, stating that "The term LVDS is herein used to generically refer to low voltage differential signals and is not intended to be limited to any particular type of LVDS technology" ('797 Patent, col. 4:1-5). This language may support an argument that any low-voltage differential signaling path, including PCIe or USB 3.x, qualifies.
- Evidence for a Narrower Interpretation: The detailed description contrasts the claimed "LVDS channel" with a "PCI bus channel," describing the LVDS channel as being "more cable friendly, faster, consumes less power, and generates less noise" ('797 Patent, col. 6:42-47). This context may support an argument that the term should be limited to the specific type of point-to-point serial links contemplated at the time of invention, rather than the more complex, packet-based protocols of PCIe and modern USB.
The Term: "peripheral bridge" (from '654 Claim 23)
- Context and Importance: The complaint alleges that the Intel Platform Controller Hub (PCH) is a "peripheral bridge." The definition of this term is critical because modern computer architecture has evolved from distinct "northbridge" and "southbridge" chips to integrated PCHs and SoCs. The court's construction will determine if this claimed architectural element from the late 1990s reads on the accused Intel architecture.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The '797 patent (from the same family) describes a "north bridge" as a "PCI BRIDGE" ('797 Patent, Fig. 18, 1714). The specification describes the bridge's function as coupling the CPU main bus to other specialty buses ('797 Patent, col. 25:60-65). This functional definition could be argued to encompass the role of a modern PCH, which connects the CPU to numerous I/O interfaces.
- Evidence for a Narrower Interpretation: The patent figures consistently depict a "North Bridge" or "South Bridge" as a discrete component separate from the CPU ('769 Patent, Fig. 2). This could support a narrower construction requiring a physically separate chip, which would raise questions about whether an integrated PCH on the same package as the CPU meets the limitation.
VI. Other Allegations
- The complaint does not provide sufficient detail for analysis of indirect infringement.
- The complaint does not provide sufficient detail for analysis of willful infringement.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of process infringement: as this case is brought under 35 U.S.C. § 271(g), a key evidentiary question will be whether the foreign manufacturing process for Gigabyte's BRIX Mini PCs, as opposed to the mere functionality of the final product, performs each and every step of the asserted method claims. Does the assembly process involve affirmative acts of "connecting," "providing," and "configuring" in the manner claimed?
- A second central issue will be one of technological scope: can claim terms rooted in the technological context of the late 1990s and early 2000s, such as "LVDS channel" and "peripheral bridge," be construed to cover the distinct and more complex architectures of modern standards like PCIe, USB 3.x, and the integrated Intel Platform Controller Hub (PCH)?
- A third question will be one of claim differentiation: particularly for the '769 patent, does providing a single, multi-protocol physical connector like USB-C satisfy the limitations of providing a "first LVDS channel" for one data type and a "second LVDS channel" for another, or does the claim language require physically or logically distinct channels?