Collabo Innovations Inc v. Qualcomm Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Collabo Innovations, Inc. (Delaware)
  • Defendant: Qualcomm Incorporated and Qualcomm Technologies, Inc. (both Delaware)
  • Plaintiff’s Counsel: Nelson Bumgardner Conroy PC
• Case Identification: 6:24-cv-00472, W.D. Tex., 09/13/2024
• Venue Allegations: Plaintiff alleges venue is proper based on Defendants maintaining regular and established places of business within the Western District of Texas, specifically two office locations in Austin, and having committed acts of infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant’s processors featuring low-power states and power collapse functionality infringe a patent related to controlling power shutdown and restoration processes in microcontrollers.
• Technical Context: The technology concerns power management methods in integrated circuits designed to minimize energy consumption during idle periods while enabling rapid resumption of full operation, a critical capability for battery-powered mobile devices.
• Key Procedural History: The complaint alleges that Plaintiff sent a letter to Defendant prior to filing the lawsuit, notifying Defendant of the alleged infringement and the need for a license.

Case Timeline

Date	Event
2006-09-12	U.S. Patent No. 7,930,575 Priority Date
2011-02-XX	Date of news release cited for Snapdragon chipset family
2011-04-19	U.S. Patent No. 7,930,575 Issue Date
2024-09-13	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,930,575 - "Microcontroller for Controlling Power Shutdown Process"

The Invention Explained

• Problem Addressed: The patent background describes that as semiconductor manufacturing has advanced, leakage current in transistors has become a significant source of power consumption, even when a microcontroller is in a conventional "stop mode." A full power shutdown eliminates this leakage but destroys the processor's internal state, necessitating a time-consuming initialization process to resume operation (’575 Patent, col. 1:25-40).
• The Patented Solution: The invention proposes a method to achieve the power savings of a full shutdown while enabling a fast restoration. It uses a "power supply control unit" that, upon detecting a "power shutdown factor," sends a request to the CPU. The CPU then executes a "power shutdown microprogram" to save its essential operating state (e.g., program counter, status registers) to an "information holding unit" (like a small RAM) that remains powered. Once the information is saved, the CPU signals completion, and the "power supply control unit" cuts power to the CPU itself, thereby minimizing leakage current while preserving the state for a quick restart (’575 Patent, Abstract; col. 2:27-67; FIG. 1).
• Technical Importance: This technique seeks to combine the benefits of very low power consumption with high-speed restoration from a standby state, a critical trade-off in the design of battery-operated electronics (’575 Patent, col. 2:53-57).

Key Claims at a Glance

• The complaint asserts independent claim 1 and reserves the right to assert additional claims (Compl. ¶25, fn. 5).
• The essential elements of independent claim 1 include:
  • a CPU;
  • a power supply unit arranged between the CPU and a power supply device;
  • a power supply control unit for controlling the CPU and the power supply unit;
  • an information holding unit for holding evacuated information from the CPU;
  • a clock generator;
  • wherein the power supply control unit outputs a shutdown request signal to the CPU in response to a power shutdown factor;
  • wherein the CPU executes a power shutdown microprogram to evacuate the necessary information to the information holding unit and then outputs an evacuation completed signal; and
  • wherein the power supply control unit receives the evacuation completed signal and then outputs a power shutdown control signal to the power supply unit.

III. The Accused Instrumentality

Product Identification

The complaint identifies "Qualcomm processors such as the Qualcomm Snapdragon 600 Processor APQ8064 and other processors and platforms offered and sold by Qualcomm that support low power state with power collapse (and similar functionality)" as the Accused Instrumentalities (Compl. ¶10).

Functionality and Market Context

The Accused Instrumentalities are alleged to be systems-on-a-chip (SoCs) that function as microcontrollers in mobile devices (Compl. ¶27). The complaint, citing Qualcomm technical documents, describes the Snapdragon 600 processor as having multiple CPU cores (Krait and QDSP6) and supporting several low-power sleep modes, including "Core power-supply voltage collapsed" and "Full IC power collapse" (Compl. ¶¶28, 29). These modes are allegedly managed by a "Resource and power manager (RPM)" which controls system resources, clock rates, and supply voltages to reduce power consumption (Compl. ¶30, p. 14). A product brief diagram illustrates the functional blocks of the Snapdragon 600 processor, including the Krait CPU, Adreno GPU, and Hexagon DSP (Compl. p. 10).

IV. Analysis of Infringement Allegations

’575 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a CPU;	The Qualcomm Snapdragon 600 processor is alleged to comprise a CPU, including four Krait mP cores and one QDSP6 core.	¶28	col. 8:40-41
a power supply unit arranged between the CPU and a power supply device for supplying power to the CPU;	The Snapdragon 600 processor is alleged to include power and sleep control features that constitute a power supply unit receiving power from an external device and supplying it to the processor cores.	¶29	col. 8:45-49
a power supply control unit for controlling the CPU and the power supply unit;	The Resource and Power Manager (RPM) and Subsystem Power Manager (SPM) within the Snapdragon 600 processor are alleged to be a control unit that controls power delivery to components.	¶30	col. 8:41-42
an information holding unit for holding information evacuated from the CPU, the information being necessary in proceeding with a program;	The L1/L2 cache in the LPASS and Krait cores are alleged to be an information holding unit where memory and logic states are preserved during power collapse modes.	¶31	col. 8:42-44
a clock generator;	The Snapdragon 600 processor is alleged to include a clock generator, as shown in its clock architecture, which includes a Krait mP Clock Block and an Audio Clock Block. A clock architecture diagram shows the interconnections of various clock blocks (Compl. p. 18).	¶32	col. 8:42
the power supply control unit outputs a shutdown request signal to the CPU in response to an occurrence of a power shutdown factor,	The RPM is alleged to initiate entry into low power modes, including power collapse, which constitutes outputting a shutdown request signal.	¶33	col. 8:56-59
the CPU, upon receiving the shutdown request signal, executes a power shutdown microprogram, evacuates the information necessary in proceeding with the program to the information holding unit, and outputs an evacuation completed signal to the power supply control unit after evacuation is completed,	It is alleged that upon receiving the shutdown request, the CPU executes a power shutdown microprogram to evacuate necessary information to the information holding unit (e.g., cache) for sleep modes involving power collapse, and then outputs an evacuation completed signal.	¶34	col. 8:60-67
the power supply control unit, upon receiving the evacuation completed signal, outputs a power shutdown control signal to the power supply unit,	It is alleged that upon receiving the evacuation completed signal, the RPM/SPM outputs a power shutdown control signal to the power supply unit to instruct it to enter a full IC power collapse state.	¶35	col. 9:1-5

Identified Points of Contention

• Scope Questions: The complaint alleges that the on-chip Resource and Power Manager (RPM) is the claimed "power supply control unit" (Compl. ¶30). However, it also presents evidence that the RPM sends commands to a Power Management IC (PMIC) to initiate shutdown (Compl. p. 20). This raises the question of whether the functionality of the claimed "power supply control unit" is performed by the accused processor alone, or if it is distributed between the on-chip RPM and an external PMIC, which may place some functions outside the scope of the accused "microcontroller."
• Technical Questions: What evidence does the complaint provide for the existence of a "power shutdown microprogram" that is actively executed by the CPU, as opposed to a hardware-managed state-saving process? The complaint alleges this step occurs (Compl. ¶34) but primarily cites technical documents that describe the outcomes of sleep modes (e.g., "Memory contents are retained") rather than detailing a specific microprogram execution sequence or an "evacuation completed signal."

V. Key Claim Terms for Construction

• The Term: "microcontroller"

• Context and Importance: The accused products are complex Systems-on-a-Chip (SoCs). The case may turn on whether these SoCs fit the patent's meaning of "microcontroller." Practitioners may focus on this term because the technological gap between a 2006-era microcontroller and a modern SoC could be a central non-infringement argument.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent does not provide an explicit definition, referring generally to a device with a "CPU 1," "power supply control unit 2," and peripheral circuits, a description that could be argued to encompass any integrated circuit with a processor and control logic (’575 Patent, FIG. 1, col. 8:40-45).
  • Evidence for a Narrower Interpretation: The specification discusses "a general microcontroller" in the context of known "stop modes" from the pre-2006 era (’575 Patent, col. 1:22-23). The diagrams consistently depict a relatively simple, self-contained architecture, which might be used to argue that the term implies a device less complex than a modern multi-core SoC that works in conjunction with an external PMIC.

• The Term: "power shutdown microprogram"

• Context and Importance: A key step of the asserted claim is the CPU's execution of this program. The infringement theory depends on mapping the accused processor's power-down sequence to this specific limitation.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent describes a microprogram as a "control program for controlling internal sources of the CPU" (’575 Patent, col. 9:48-51). This language could support a broad interpretation covering any set of executable instructions or even hard-coded logic that orchestrates the evacuation of information.
  • Evidence for a Narrower Interpretation: The patent's flowcharts show the activation of the "power shutdown microprogram" as a discrete step (e.g., ’575 Patent, FIG. 2, step n2). This, combined with the term "microprogram" itself, may suggest a specific type of firmware or software routine is required, rather than an automatic, hardware-driven state-saving mechanism that lacks an explicit execution step by the CPU.

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement, asserting that Qualcomm knowingly encourages infringement by its customers and partners. This is allegedly done through the creation and distribution of materials like product briefs and device specifications, which instruct on how to use the accused power-saving features (Compl. ¶¶41-42).
• Willful Infringement: The complaint alleges willful infringement based on both pre-suit and post-suit knowledge. It claims Qualcomm had pre-suit knowledge from a notification letter sent by Collabo (Compl. ¶18) and post-suit knowledge from the filing of the complaint itself (Compl. ¶42).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of architectural mapping: Can the functions of the claimed "power supply control unit" and "power supply unit" be found within the accused "microcontroller" (the SoC), or is the control of power shutdown in the accused system fundamentally distributed between on-chip logic (the RPM) and a separate, external Power Management IC (PMIC), potentially placing key functions outside the claim scope?
• A key evidentiary question will be one of functional mechanism: Does the accused processor's method for entering a low-power state involve the CPU executing a "power shutdown microprogram" and issuing a subsequent discrete signal as claimed, or is it a hardware-managed process that achieves a similar result without performing the specific, sequential steps required by the patent?