DCT

6:25-cv-00520

Powerwatch Systems LLC v. HP Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:25-cv-00520, W.D. Tex., 10/30/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant HP Inc. has transacted business, committed acts of infringement, and maintains a regular and established place of business in the district, including an Austin storefront with over 150 employees and a local data center.
  • Core Dispute: Plaintiff alleges that Defendant’s computer products, including workstations, desktops, and servers containing certain memory components, infringe seven patents related to fundamental semiconductor design, manufacturing, and operation.
  • Technical Context: The patents-in-suit address various aspects of semiconductor technology, including memory cell structure, data access speed, clock signal synchronization, and I/O pin drive strength, which are foundational to the performance of modern memory and computing devices.
  • Key Procedural History: The complaint states that all seven asserted patents have been the subject of prior litigation, including district court cases and Inter Partes Review (IPR) proceedings at the Patent Trial and Appeal Board. Plaintiff asserts that the scope and construction of the claims have been clarified by these prior actions. The complaint also references a 2019 lawsuit by a prior patent owner against memory chip supplier Nanya Technologies Corp., which allegedly resulted in a settlement but did not grant a license to Nanya's customers, such as HP.

Case Timeline

Date Event
2000-05-12 U.S. Patent No. 6,366,145 Priority Date
2001-07-20 U.S. Patent No. 6,573,753 Priority Date
2002-03-29 U.S. Patent No. 6,979,640 Priority Date
2002-12-06 U.S. Patent No. 6,680,516 Priority Date
2003-03-26 U.S. Patent No. 7,158,429 Priority Date
2003-10-10 U.S. Patent No. 6,963,108 Priority Date
2004-01-16 U.S. Patent No. 6,825,526 Priority Date
2019-04-23 Alleged first notice of infringement sent to Defendant
2019-11-04 Prior patent owner filed lawsuit against Nanya Technologies Corp.
2020-05-22 Alleged follow-up notice of infringement sent to Defendant
2020-12-21 U.S. Patent No. 6,366,145 Expired
2021-07-20 U.S. Patent No. 6,573,753 Expired
2022-03-29 U.S. Patent No. 6,979,640 Expired
2022-12-06 U.S. Patent No. 6,680,516 Expired
2023-10-10 U.S. Patent No. 6,963,108 Expired
2024-01-16 U.S. Patent No. 6,825,526 Expired
2024-08-15 U.S. Patent No. 7,158,429 Expired
2025-10-30 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,680,516 - "CONTROLLED THICKNESS GATE STACK"

The Invention Explained

  • Problem Addressed: The patent’s background describes a challenge in shrinking semiconductor devices: as device elements become smaller, the vertical passages (contact vias) used for electrical connections must have large aspect ratios (height vs. width), which can make them difficult to fill properly, potentially leading to faulty circuits (Compl. ¶18; ’516 Patent, col. 1:53-61).
  • The Patented Solution: The invention proposes a specific multi-layer semiconductor structure, or "gate stack," with precisely controlled thicknesses. This stack includes a gate layer, a metallic layer, and an etch-stop layer, with a total height of at most 2700 angstroms, designed to enable the reliable formation of smaller contact vias with more manageable aspect ratios (Compl. ¶19; ’516 Patent, Abstract, col. 2:1-6).
  • Technical Importance: This approach sought to facilitate continued miniaturization of integrated circuits by resolving a key manufacturing obstacle related to the reliability of inter-layer electrical connections (Compl. ¶32; ’516 Patent, col. 1:41-45).

Key Claims at a Glance

  • The complaint asserts independent claims 5 and 10, and dependent claim 7 (Compl. ¶103).
  • The essential elements of independent claim 5 include:
    • A semiconductor structure comprising a substrate, gate layer, metallic layer, etch-stop layer, and an insulating layer.
    • A via through the insulating layer to the substrate.
    • A via width of at most 0.12 micron.
    • A "gate stack height," defined as the distance from the substrate to the top of the etch-stop layer, of at most 2700 angstroms.
  • The complaint reserves the right to assert additional claims (Compl. ¶104).

U.S. Patent No. 6,825,526 - "STRUCTURE FOR INCREASING DRIVE CURRENT IN A MEMORY ARRAY AND RELATED METHOD"

The Invention Explained

  • Problem Addressed: In conventional flash memory, increasing the drive current to achieve faster data access speeds required widening the memory cell’s channel, which undesirably increased the overall size and reduced the density of the memory array (Compl. ¶20; ’526 Patent, col. 1:39-45).
  • The Patented Solution: The invention describes a memory array structure that incorporates a trench within the substrate between isolation regions. This trench increases the three-dimensional surface area available for the channel, thereby increasing the "effective channel width" and drive current without increasing the horizontal footprint of the cell (Compl. ¶21; ’526 Patent, Abstract, col. 2:5-13).
  • Technical Importance: This technology allowed memory designers to increase access speed without sacrificing storage density, addressing a critical trade-off in the development of high-performance memory components (Compl. ¶34; ’526 Patent, col. 1:53-58).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶111).
  • The essential elements of independent claim 1 include:
    • A memory array with first and second isolation regions in a substrate separated by a "separation distance."
    • A trench situated between the isolation regions, defining trench sidewalls and a bottom.
    • A tunnel oxide layer on the trench sidewalls and bottom.
    • A channel region underneath the tunnel oxide layer having an "effective channel width."
    • The "effective channel width" is greater than the "separation distance" between the isolation regions.
  • The complaint reserves the right to assert additional claims (Compl. ¶112).

U.S. Patent No. 7,158,429 - "SYSTEM FOR READ PATH ACCELERATION"

Technology Synopsis

The patent addresses the problem of data corruption that can occur when transmitting signals at high speeds over long distances within an integrated circuit (Compl. ¶22). The proposed solution is a memory architecture where the memory core is divided into segments, each with local amplifiers, which are coupled to a main amplifier to accelerate the data read path while maintaining signal integrity (Compl. ¶23).

Asserted Claims

At least claims 2-3 are asserted (Compl. ¶119).

Accused Features

The complaint accuses infringing memory cell components in HP’s products of practicing this read path acceleration system (Compl. ¶119).

U.S. Patent No. 6,573,753 - "MICROCONTROLLER INPUT/OUTPUT NODES WITH BOTH PROGRAMMABLE PULL-UP AND PULL-DOWN RESISTIVE LOADS AND PROGRAMMABLE DRIVE STRENGTH"

Technology Synopsis

The patent addresses the need for more nuanced control over the electrical drive strength of a microcontroller’s input/output (I/O) pins to operate reliably in hostile or dynamic electrical environments (Compl. ¶24). The invention is an I/O node with multiple programmable pull-up and pull-down resistors that can be selectively activated by logic to provide variable drive strengths (e.g., strong, medium, or weak) (Compl. ¶25).

Asserted Claims

At least claim 1 is asserted (Compl. ¶127).

Accused Features

The complaint accuses memory components, such as those with DDR3 or later versions featuring ZQ calibration, which allows for adjusting I/O driver strength (Compl. ¶¶93, 127).

U.S. Patent No. 6,366,145 - "LINEARIZED DIGITAL PHASE-LOCKED LOOP"

Technology Synopsis

The patent addresses excessive jitter in conventional "bang-bang" phase-locked loops (PLLs) used for clock signal recovery, which made corrections based only on the polarity of phase error (Compl. ¶26). The invention describes a PLL with a detector that produces a value representing the magnitude and position of a data signal's edge relative to the clock, enabling a control circuit to make more precise, linearized adjustments to the clock signal (Compl. ¶27).

Asserted Claims

At least claims 1 and 11 are asserted (Compl. ¶135).

Accused Features

The complaint accuses memory components used in HP products that perform clock and data signal synchronization (Compl. ¶135).

U.S. Patent No. 6,979,640 - "CONTACT STRUCTURE AND METHOD OF MAKING THE SAME"

Technology Synopsis

The patent addresses the problem of misaligned contacts (vias) in shrinking semiconductor devices, which limited further miniaturization (Compl. ¶28). It discloses a method of making a contact structure using an etch-stop layer with a specific thickness relative to the conducting layer’s line width, providing greater flexibility in the structure and reducing the risk of misalignment (Compl. ¶29).

Asserted Claims

At least claims 1 and 2 are asserted (Compl. ¶143).

Accused Features

The complaint accuses the infringing memory cell components used in HP products of being made by an infringing process (Compl. ¶143).

U.S. Patent No. 6,963,108 - "RECESSED CHANNEL"

Technology Synopsis

The patent addresses performance degradation, charge loss, and leakage problems (known as short channel effects) that arise from downscaling transistors (Compl. ¶30). The invention is a memory cell with a channel region recessed into a trench, located below the source and drain regions, which alters the transistor geometry to mitigate these adverse effects (Compl. ¶31).

Asserted Claims

At least claim 1 is asserted (Compl. ¶151).

Accused Features

The complaint accuses DRAM components using Recessed Channel Array Transistor (RCAT) technology of infringement (Compl. ¶¶93, 151).

III. The Accused Instrumentality

Product Identification

The complaint identifies two categories of accused items: "Accused Instrumentalities," which are memory components, and "Accused Products," which are HP hardware systems incorporating those components (Compl. ¶93, ¶95). Specific HP product lines named include Z Workstations, EliteDesk/Prodesk desktops, OMEN/ENVY desktops, ProLiant Servers, and certain HP solid-state drives (SSDs) (Compl. ¶95).

Functionality and Market Context

The allegations focus on the technical features of memory components used within HP's products, particularly those sourced from third parties such as Nanya, HyperX, Kingston, and VisionTek (Compl. ¶¶93-94). The accused functionalities are specific semiconductor technologies, including: DDR3 or later memory versions with ZQ calibration and ODT capabilities; DRAM manufactured at 75nm, 42nm, or smaller process nodes; and DRAM utilizing Recessed Channel Array Transistor (RCAT) technology (Compl. ¶93). The complaint asserts these memory technologies are commercially successful and integral to modern computing systems (Compl. ¶49).

IV. Analysis of Infringement Allegations

The complaint references claim chart exhibits for each asserted patent (e.g., Exhibit 1B for the ’516 Patent) but does not include these exhibits in the filing (Compl. ¶104, ¶112). The narrative infringement allegations are summarized below. No probative visual evidence provided in complaint.

’516 Patent Infringement Allegations

The complaint alleges that HP's products incorporate memory components that are manufactured with a "Controlled Thickness Gate Stack" meeting the limitations of at least claims 5, 7, and 10 of the ’516 Patent (Compl. ¶103). The infringement theory is based on the physical structure of the semiconductor devices, which are alleged to possess the claimed arrangement of substrate, gate, metallic, and etch-stop layers with dimensions falling within the claimed ranges, such as a gate stack height of at most 2700 angstroms and a via width of at most 0.12 micron (Compl. ¶19; ’516 Patent, col. 9:10-20).

’526 Patent Infringement Allegations

The complaint alleges that accused memory arrays directly infringe at least claim 1 of the ’526 Patent (Compl. ¶111). The theory of infringement posits that these memory arrays are built with a trench structure between isolation regions, a design which allegedly results in an "effective channel width" that is greater than the "separation distance" between those regions, thereby matching the core elements of claim 1 (Compl. ¶21; ’526 Patent, col. 6:23-34).

Identified Points of Contention

  • Scope Questions: For the ’526 Patent, a central question may be whether the term "trench," as described in the patent for increasing channel surface area, can be construed to read on the structures used in modern, high-density DRAM, which may achieve performance goals through different architectural means.
  • Technical Questions: For the ’516 Patent, the dispute may center on precise, physical measurements. A key question for the fact-finder will be whether reverse engineering of the accused memory chips confirms that their gate stack layers meet the specific numerical limitations required by the claims, such as the "at most 2700 angstroms" height.

V. Key Claim Terms for Construction

  • Term: "gate stack height" (’516 Patent, Claim 5)

    • Context and Importance: This term is tied to a specific numerical limit ("at most 2700 angstroms"), making its definition critical to the infringement analysis. Practitioners may focus on the precise start and end points for this measurement, as minor variations in methodology could determine whether an accused product falls inside or outside the claim scope.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The claim itself defines the term as "a distance between the substrate and a top of the etch-stop layer," language which may support a straightforward vertical measurement between the two specified surfaces (’516 Patent, col. 9:18-20).
      • Evidence for a Narrower Interpretation: The specification’s focus on solving problems related to the aspect ratio of contact vias could support an argument that the measurement should be interpreted in a manner most relevant to that technical context, potentially excluding layers or features not pertinent to via formation (’516 Patent, col. 5:22-34).

  • Term: "effective channel width" (’526 Patent, Claim 1)

    • Context and Importance: The invention's core concept rests on achieving an "effective channel width" that is "greater than said separation distance." The definition of this term will be dispositive. The dispute will likely involve whether this term has a purely geometric meaning or a more complex electrical one.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification describes the effective channel width in geometric terms, corresponding to the length of the tunnel oxide layer along the profile of the trench, including its sidewalls and bottom (’526 Patent, col. 5:29-44).
      • Evidence for a Narrower Interpretation: Parties may argue that "effective channel width" is a term of art that refers to the electrical characteristics of the channel, not just its physical dimensions. An argument could be made that not all of the trench’s surface area contributes to the effective width in the manner required by the claim, particularly in advanced transistor designs not contemplated by the patent.

VI. Other Allegations

  • Indirect Infringement: The complaint makes a general allegation of induced infringement, stating that HP encourages infringement by "creating and/or disseminating product information and other materials providing instruction for infringing use" (Compl. ¶10).
  • Willful Infringement: Willfulness is alleged for all seven patents. The basis for this allegation is purported pre-suit knowledge of the patents and infringement, stemming from notice letters allegedly sent to HP by the prior patent owner on April 23, 2019, and May 22, 2020 (Compl. ¶¶96-97, 105, 113).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of technical correspondence: will forensic analysis of the accused memory chips, which are modern components, reveal the specific structures and dimensional limitations claimed in patents filed in the early 2000s? For example, does the accused DRAM practice the precise "recessed channel" of the ’108 patent, or does it use a more advanced, non-infringing design?
  • A second key question will be the impact of prior adjudications: with all asserted patents having an extensive history of litigation and PTAB reviews, the case may turn on whether HP's accused products can be distinguished from the claims as they have been previously construed and challenged. The applicability of claim construction rulings and invalidity findings from those prior cases will be a central legal battleground.
  • A third question concerns license rights and patent exhaustion: does the prior settlement agreement between the former patent owner and chip supplier Nanya Technologies create a defense for HP, a downstream customer? The court will need to analyze the terms of that agreement to determine if any license rights, express or implied, flow to purchasers of Nanya's products, notwithstanding the complaint's assertion to the contrary.