DCT

6:25-cv-00581

Bayerische Motoren Werke Aktiengesellschaft v. Onesta IP LLC

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:25-cv-00581, W.D. Tex., 12/15/2025
  • Venue Allegations: Plaintiff BMW AG asserts venue is proper because Defendant Onesta IP has directed patent enforcement activities into the district, including filing other lawsuits, and is therefore subject to personal jurisdiction and "resides" in the district for venue purposes.
  • Core Dispute: Plaintiff seeks a declaratory judgment of patent misuse, noninfringement, and invalidity of two U.S. patents related to computer processing, which Defendant has asserted against Plaintiff in a German court.
  • Technical Context: The patents-in-suit concern methods for managing tasks and power in high-performance processors like Graphics Processing Units (GPUs), technology central to modern automotive infotainment and driver-assistance systems.
  • Key Procedural History: This action arises from Defendant’s assertion of U.S. patents against Plaintiff in the Munich Regional Court I in Germany. Plaintiff characterizes this as improper extraterritorial enforcement. One of the patents-in-suit, U.S. Patent No. 8,854,381, has a significant litigation history, including prior findings of invalidity for certain claims by an ITC Administrative Law Judge and a since-terminated Inter Partes Review proceeding at the Patent Trial and Appeal Board where trial was instituted.

Case Timeline

Date Event
2009-07-24 U.S. Patent No. 8,443,209 Priority Date
2009-09-03 U.S. Patent No. 8,854,381 Priority Date
2013-05-14 U.S. Patent No. 8,443,209 Issue Date
2014-10-07 U.S. Patent No. 8,854,381 Issue Date
2018-04-14 Alleged start of damages period for ’381 Patent in German case
2022-05-05 ITC Investigation No. 337-TA-1318 filed concerning ’381 Patent
2023-03-07 IPR Petition (IPR2023-00687) filed against ’381 Patent
2023-07-07 ITC ALJ issues Initial Determination finding claims of ’381 Patent invalid
2023-10-25 PTAB institutes trial in IPR against ’381 Patent
2024-06-26 PTAB terminates IPR against ’381 Patent due to settlement
2024-11-08 Advanced Micro Devices, Inc. allegedly assigns ’381 Patent to Onesta
2025-04-17 Onesta files WDTX Litigations concerning ’381 Patent
2025-04-18 Onesta files ITC Complaint (Inv. No. 337-TA-1450) concerning ’381 Patent
2025-10-09 Onesta files suit against BMW AG in Munich, Germany
2025-12-15 Complaint for Declaratory Judgment filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,854,381: Processing unit that enables asynchronous task dispatch (Issued Oct. 7, 2014)

The Invention Explained

  • Problem Addressed: The patent addresses the inefficiency of conventional Graphics Processing Units (GPUs) when handling tasks of mixed priorities. When a high-priority, low-latency task arrives, a conventional GPU must perform a time-consuming "context switch" to pause an ongoing task, a process that requires substantial time and additional local memory, making the GPU ineffective for truly time-sensitive operations ('381 Patent, col. 2:11-60).
  • The Patented Solution: The invention describes a processing unit architecture featuring multiple "virtual engines" that can receive tasks in parallel from an operating system scheduler and feed them to a single "shader core" ('381 Patent, Figs. 3A-3B). This shader core is configured to execute multiple tasks—such as a high-priority task and a standard-priority task—"substantially in parallel" by loading their respective state data without a full, disruptive context switch, enabling efficient handling of concurrent, mixed-priority workloads ('381 Patent, Abstract; col. 3:1-12).
  • Technical Importance: This architecture allows a single processing unit to manage concurrent streams of high-priority and background computational tasks more efficiently, a capability critical for complex interactive systems found in modern computing and automotive applications ('381 Patent, col. 2:5-9).

Key Claims at a Glance

  • The complaint seeks a declaratory judgment of noninfringement for claims 1-6 and 15-20 (Compl. ¶113). The primary focus is on independent claim 1.
  • Independent Claim 1 recites an apparatus comprising:
    • a plurality of engines configured to receive a plurality of tasks from a scheduling module and to load state data for each task; and
    • a shader core configured to receive the tasks from the engines and "to execute a first task from the plurality of tasks while executing a second task from the plurality of tasks based on respective state data."

U.S. Patent No. 8,443,209: Throttling computational units according to performance sensitivity (Issued May 14, 2013)

The Invention Explained

  • Problem Addressed: The patent confronts the inefficiency of power allocation in multi-core processors. Prior methods for boosting performance often treat all active processing cores "homogeneously," applying power boosts equally without regard for the specific workload. This is suboptimal because some tasks gain significant performance from increased frequency while others see little benefit, wasting power ('209 Patent, col. 1:40-48).
  • The Patented Solution: The invention discloses a power allocation strategy based on analyzing the "performance sensitivity" of each computational unit to a change in its performance capability (e.g., frequency) ('209 Patent, Abstract). The system identifies the subset of units that are least sensitive to such a change, limits their performance (throttles them), and reallocates the saved power headroom to more sensitive units, thereby maximizing overall system throughput for a given thermal design point (TDP) ('209 Patent, col. 2:27-44).
  • Technical Importance: This method enables more intelligent, workload-aware dynamic power management in complex Systems-on-Chip (SoCs), improving performance and efficiency in power-constrained environments like mobile devices and vehicle electronics ('209 Patent, col. 2:44-48).

Key Claims at a Glance

  • The complaint seeks a declaratory judgment of noninfringement for claims 1, 5-6, 8, 10, 11, 13, and 15-18 (Compl. ¶123). The primary focus is on independent claim 1.
  • Independent Claim 1 recites a method comprising:
    • accessing performance data indicative of performance sensitivity of each of a plurality of computational units... to a change in performance capability;
    • determining a subset of... computational units... that are least sensitive to the change... based on the performance data; and
    • limiting performance of the subset... in the computer system.

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are certain BMW vehicles, including the BMW i4, that are equipped with a Qualcomm Snapdragon System-on-Chip (SoC) featuring an integrated Adreno GPU (Compl. ¶¶ 42, 79). Specifically, the complaint identifies the "Head Unit High 5 (HU-H5)" which allegedly uses the Qualcomm Snapdragon SoC SA8155P with an integrated Adreno 640 GPU (Compl. ¶¶ 113, 123).

Functionality and Market Context

The complaint alleges these components are part of BMW's vehicle systems and describes BMW as a "global leader in automotive innovation, luxury, and engineering" (Compl. ¶26). The complaint does not provide sufficient detail for analysis of the specific technical operation of the accused SoCs. Instead, it makes conclusory denials of infringement, asserting that the components do not operate in the manner required by the patent claims (Compl. ¶¶ 117, 127).

IV. Analysis of Infringement Allegations

The complaint does not provide a detailed infringement analysis or claim chart but instead presents a narrative theory of noninfringement for each patent.

’381 Patent Non-Infringement Allegations

The complaint’s central theory of noninfringement is a direct factual denial of a key claim limitation. Plaintiff alleges that its vehicles and the components therein "do not comprise a shader cord [core] associated with a first processing unite [unit] that executes a first task from the plurality of tasks while executing a second task from the plurality of tasks" as required by claim 1 (Compl. ¶117). This suggests the core of the dispute will be a factual and technical one regarding the operational capabilities of the Adreno 640 GPU. While the non-infringement allegations are sparse, the complaint provides extensive invalidity arguments against the ’381 Patent, supported by visual evidence from prior art references (Compl. ¶¶ 136-143). For example, the complaint reproduces a block diagram from a prior art patent to illustrate a graphics system alleged to anticipate the claimed invention (Compl. p. 21, ¶137).

  • Identified Points of Contention:
    • Technical Question: Does the accused Adreno 640 GPU, in its normal operation within BMW vehicles, execute multiple tasks from different processing streams concurrently on a single shader core? The case may turn on evidence of the GPU's internal architecture and task scheduling mechanisms.
    • Scope Question: How broadly will the phrase "execute a first task... while executing a second task" be construed? Does it require true, simultaneous, parallel hardware execution, or could it be read to cover rapid time-multiplexing that achieves a similar functional outcome?

’209 Patent Non-Infringement Allegations

Plaintiff’s non-infringement argument is a denial that the accused products perform the specific three-step method of claim 1. The complaint alleges the accused components do not: (1) access performance data indicative of performance sensitivity, (2) determine a subset of computational units that are "least sensitive" based on that data, or (3) limit the performance of that specific subset (Compl. ¶127). This denial frames the dispute around the specific algorithm used by the Qualcomm SoC for power management. The complaint also presents detailed invalidity arguments against this patent, including a figure from the "Ghiasi" prior art reference depicting a flowchart of a power management system alleged to teach the claimed method (Compl. p. 41, ¶153).

  • Identified Points of Contention:
    • Technical Question: What power management algorithm does the accused Qualcomm Snapdragon SoC actually implement? Discovery will likely focus on whether its logic matches the specific "access, determine least sensitive, limit" sequence required by the claim.
    • Scope Question: Does the SoC's power management system, even if it does not explicitly calculate "performance sensitivity" as described in the patent's specification, use functionally equivalent data and logic to identify and throttle underperforming units in a way that meets the claim limitations under the doctrine of equivalents?

V. Key Claim Terms for Construction

’381 Patent: "execute a first task... while executing a second task"

  • Context and Importance: This phrase is the central limitation describing the concurrent operation of the shader core and is the focus of Plaintiff's noninfringement argument. Its construction will determine whether the accused GPU's method of handling multiple task streams falls within the scope of the claim.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the execution as occurring "substantially in parallel" and "(substantially) simultaneously," language which may support a construction that includes not only true hardware parallelism but also very rapid, interleaved processing that is functionally concurrent (Compl. ¶117; '381 Patent, col. 3:8, col. 9:60-61).
    • Evidence for a Narrower Interpretation: The patent also describes partitioning the shader core's resources in space, such as by issuing different tasks to different subsets of processing elements (SIMDs). This could support a narrower construction requiring physically distinct, parallel execution paths within the single shader core ('381 Patent, col. 5:14-22, col. 8:9-17).

’209 Patent: "performance sensitivity"

  • Context and Importance: This term defines the type of data used to make the throttling decision. Whether the accused system "accesses" data meeting this definition is critical to the infringement analysis. Practitioners may focus on this term because its definition could be tied to a specific method of measurement disclosed in the patent.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The term could be construed broadly to encompass any metric that reflects how a processor's performance changes with frequency or voltage, potentially including general workload or utilization data that an accused system might already collect for other purposes ('209 Patent, col. 2:30-33).
    • Evidence for a Narrower Interpretation: The specification describes a specific "training" process for determining this value, which involves applying low and high frequency signals and measuring the difference in instructions per second (IPS) ('209 Patent, col. 4:22-49). This detailed example could support a narrower construction limiting the term to data derived from such a differential measurement or a similar explicit characterization.

VI. Other Allegations

  • Patent Misuse: The complaint alleges that Defendant has misused both the ’381 and ’209 Patents. The theory of misuse is based on Defendant's assertion of its U.S. patents against Plaintiff in a German court (Compl. ¶¶ 42-43, 79-80). Plaintiff alleges this constitutes an "improper broadening of the physical, temporal, and/or adjudicative scope of the exclusionary rights" granted by a U.S. patent and has an anticompetitive effect in the U.S. market (Compl. ¶¶ 48, 73-74, 85, 107-108).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A threshold issue will be one of jurisdiction and legal theory: can a patent holder’s enforcement of its U.S. patents in a foreign court provide the basis for a declaratory judgment action and a claim of patent misuse in a U.S. court, or is this an issue beyond the scope of U.S. patent law?
  • A central technical question will be one of operational concurrency: does the accused Adreno 640 GPU’s architecture factually meet the ’381 Patent’s claim requirement of executing a first task "while executing" a second task on a single shader core, or does it use a fundamentally different method for handling multiple task streams?
  • A key evidentiary question will be one of algorithmic equivalence: does the power management logic in the accused Qualcomm Snapdragon SoC perform the specific three-step method of the ’209 Patent—accessing sensitivity data, determining the least sensitive units, and limiting that subset—or does it rely on a distinct, non-infringing heuristic for managing power?