DCT
7:24-cv-00262
Palisade Tech LLP v. Micron Technology Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Palisade Technologies, LLP (Nevada)
- Defendant: Micron Technology, Inc. (Delaware) and Micron Semiconductor Products, Inc. (Idaho)
- Plaintiff’s Counsel: Nelson Bumgardner Conroy PC; Cherry Johnson Siegmund James PLLC
- Case Identification: 7:24-cv-00262, W.D. Tex., 12/19/2024
- Venue Allegations: Plaintiff alleges venue is proper because Defendants maintain a regular and established place of business within the district and have committed acts of patent infringement in the district.
- Core Dispute: Plaintiff alleges that Defendant’s semiconductor memory devices, including DRAM and 3D NAND flash memory products, infringe five patents related to voltage regulation, 3D memory structure detection and manufacturing, and portable memory card design.
- Technical Context: The technologies at issue concern fundamental aspects of modern semiconductor memory design and fabrication, which are critical components in a wide range of consumer and enterprise electronics.
- Key Procedural History: The complaint alleges that Defendant had pre-suit knowledge of U.S. Patent No. 8,996,838 because a USPTO examiner cited it against one of Defendant’s patent applications in 2017, and the patent was subsequently listed on the face of an issued U.S. Patent assigned to Defendant.
Case Timeline
| Date | Event |
|---|---|
| 2007-11-20 | Priority Date for U.S. Patent No. 8,327,051 |
| 2009-05-12 | Priority Date for U.S. Patent No. 8,148,962 |
| 2012-04-03 | U.S. Patent No. 8,148,962 Issues |
| 2012-12-04 | U.S. Patent No. 8,327,051 Issues |
| 2014-05-08 | Priority Date for U.S. Patent No. 8,996,838 |
| 2014-10-10 | Priority Date for U.S. Patent No. 9,281,314 |
| 2015-03-31 | U.S. Patent No. 8,996,838 Issues |
| 2015-07-22 | Priority Date for U.S. Patent No. 9,524,974 |
| 2016-03-08 | U.S. Patent No. 9,281,314 Issues |
| 2016-12-20 | U.S. Patent No. 9,524,974 Issues |
| 2017-06-07 | ’838 Patent allegedly cited by USPTO examiner against Defendant's patent application |
| 2024-12-19 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 8,148,962 - “Transient Load Voltage Regulator”
Issued April 3, 2012
The Invention Explained
- Problem Addressed: The patent addresses the challenge of maintaining a stable supply voltage for integrated circuits (ICs) when different circuit blocks are selectively powered on or off, creating varying load conditions (Compl. ¶32; ’962 Patent, col. 1:11-24). Conventional solutions, such as source followers, are described as operating poorly at lower frequencies and often requiring large, space-consuming output capacitors to ensure stability (’962 Patent, col. 1:36-47).
- The Patented Solution: The invention proposes a voltage regulator circuit designed for improved stability without a large capacitor. The circuit uses a feedback loop to maintain a substantially constant voltage at the gate of a feedback transistor. A key element is a second current supply circuit that provides a current to a pass device, where the magnitude of this second current is based on two inputs: the stable voltage from the feedback transistor’s gate and the variable voltage at the circuit’s output. This dual-input dependency allows the regulator to react quickly to load changes (’962 Patent, Abstract; col. 2:20-52).
- Technical Importance: This design purports to achieve effective power supply regulation across a wide range of operating frequencies while minimizing the physical space required on an IC, a critical consideration for cost and miniaturization (’962 Patent, col. 4:1-10).
Key Claims at a Glance
- The complaint asserts independent Claim 1 (Compl. ¶31).
- Claim 1 requires, in part:
- A voltage regulator circuit integrated in an IC for providing voltage from a power supply to a load.
- A feedback circuit with a feedback transistor, constructed to maintain a substantially constant voltage at the gate of the feedback transistor.
- A first current supply circuit constructed to supply a substantially constant first current to a second current path.
- A second current supply circuit constructed to supply a second current to the second current path, with a magnitude based on both the voltage at the feedback transistor’s gate and the voltage at the regulator’s output.
- A pass device that receives a signal based on the current in the second current path and supplies a load current to the output.
- The complaint expressly reserves the right to assert additional claims (Compl. ¶31, fn. 1).
U.S. Patent No. 8,996,838 - “Structure Variation Detection for a Memory Having a Three-Dimensional Memory Configuration”
Issued March 31, 2015
The Invention Explained
- Problem Addressed: In the fabrication of 3D non-volatile memory, the process of etching deep "memory holes" through stacked layers of material can result in structural variations. A common variation is a "tapered" profile, where the hole is wider at the top than at the bottom, which can affect the performance characteristics of memory cells at different vertical layers (’838 Patent, col. 2:1-10).
- The Patented Solution: The patent describes a method for managing these variations. The solution involves first detecting a location associated with the variation (e.g., the vertical layer where tapering begins). This is achieved by measuring and comparing operational parameters of storage elements at different layers. The key step is then "storing information" that identifies this location. This stored information can later be "accessed" by the memory controller to apply different operational parameters (such as different error-correction schemes or programming voltages) to memory cells above and below the variation, thereby compensating for the structural differences (’838 Patent, Abstract; col. 2:10-42).
- Technical Importance: This method provides a way to improve the reliability and manufacturing yield of 3D memory devices by actively identifying and compensating for inherent, process-induced structural imperfections (’838 Patent, col. 2:10-21).
Key Claims at a Glance
- The complaint asserts independent Claim 1, a method claim (Compl. ¶52).
- Claim 1 requires the steps of:
- In a data storage device with a 3D memory configuration including a structure extending through multiple layers:
- storing information at the data storage device, where the information identifies a location associated with a variation of the structure; and
- accessing the information.
- The complaint expressly reserves the right to assert additional claims (Compl. ¶31, fn. 1).
U.S. Patent No. 8,327,051 - “Portable Handheld Memory Card and Methods for Use Therewith”
Issued December 4, 2012 (Multi-Patent Capsule)
Technology Synopsis
The patent describes a portable memory card featuring both a Universal Serial Bus (USB) port and a separate input/output (I/O) port (e.g., a Secure Digital port) (Compl. ¶¶66, 68; ’051 Patent, col. 2:1-9). The invention places both ports on the same end of the card to allow for a single insertion direction into a host device, and it is configured such that when one port is electrically connected, at least one pin of the other port is not, preventing interface conflicts (’051 Patent, Abstract; col. 2:1-9).
Asserted Claims
Claim 1 (Compl. ¶65).
Accused Features
The complaint accuses portable Solid State Drives (SSDs) with a USB-C port, such as the Crucial X9, alleging they embody the claimed dual-interface functionality within a single connector positioned for a single insertion direction (Compl. ¶¶63, 72-73). The complaint's Figure on page 20 shows the exterior of the accused Crucial X9 SSD, highlighting the port (Compl. p. 20).
U.S. Patent No. 9,281,314 - “Non-Volatile Storage Having Oxide/Nitride Sidewall”
Issued March 8, 2016 (Multi-Patent Capsule)
Technology Synopsis
This patent details a method for manufacturing a non-volatile storage device to improve electrical insulation and performance. The method involves forming oxide layers on the sidewalls of both the charge storage regions and the word lines. Critically, a nitride layer is then formed that covers the oxide on the word line sidewalls but not the oxide on the charge storage region sidewalls. This selective formation prevents charge trapping in nitride material near the charge storage region, which can degrade memory cell operation (’314 Patent, Abstract).
Asserted Claims
Claim 13 (a method claim) (Compl. ¶84).
Accused Features
The complaint accuses the manufacturing method of Defendant's 3D NAND products, such as the Micron 7450 Pro (Compl. ¶82). Figure 3 in the complaint is a TEM image presented to show the accused device's control gate, charge trap film, and charge storage region sidewalls (Compl. ¶85, p. 29).
U.S. Patent No. 9,524,974 - “Alternating Sidewall Assisted Patterning”
Issued December 20, 2016 (Multi-Patent Capsule)
Technology Synopsis
The patent discloses a semiconductor structure featuring a dielectric layer with alternating trenches that have different cross-sectional shapes. For instance, a first set of trenches may have a T-shape (wider at the top), while an alternating second set of trenches has a more uniform, rectangular shape. This structural arrangement, achieved through sidewall assisted patterning, allows for the creation of features like bit lines with different profiles, potentially improving manufacturing tolerance or electrical performance (’974 Patent, Abstract).
Asserted Claims
Claim 1 (Compl. ¶100).
Accused Features
The complaint alleges that Defendant’s NAND flash memory products, including the Micron 7450 Pro, are manufactured with a structure of alternating trenches having different shapes (Compl. ¶¶98, 101). Figure 9 in the complaint is an annotated TEM image purporting to show a plurality of first and second trenches with different shapes in the accused device (Compl. ¶101, p. 37).
III. The Accused Instrumentality
Product Identification
The complaint identifies several accused product families: LPDDR5 DRAM (e.g., Micron MT62F1G64D4ZV-026 WT:B), 3D NAND flash memory with 176 or more layers (e.g., Micron 7450 Pro), and portable SSDs (e.g., Crucial X9) (Compl. ¶¶7, 29, 49, 63).
Functionality and Market Context
- The accused DRAM products incorporate on-chip voltage regulators to manage power delivery to the memory array (Compl. ¶32). The accused 3D NAND products are high-density storage devices built with a vertically stacked architecture (Compl. ¶49). The complaint alleges that to ensure reliability in these advanced 3D NAND devices, Defendant employs methods to compensate for manufacturing variations across the vertical stack by adjusting operational parameters (Compl. ¶53). The complaint includes a TEM image of the Micron 7450 to illustrate its 3D memory configuration with a structure extending through multiple layers (Compl. ¶52, p. 15, Fig. 1).
- These products represent commercially significant components in the global electronics market, used in everything from mobile devices to data centers (Compl. ¶¶2, 7).
IV. Analysis of Infringement Allegations
’962 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a voltage regulator circuit integrated in an integrated circuit (IC) and adapted to provide a voltage from a power supply to a load under varying load conditions | The accused DRAM products comprise voltage regulators integrated into the IC. | ¶32 | col. 2:20-24 |
| a feedback circuit coupled to a first current path and including a feedback transistor, wherein said feedback circuit is constructed to maintain a voltage at a gate of said feedback transistor substantially constant | The voltage regulators allegedly include a feedback circuit with a feedback transistor, where a differential amplifier maintains the voltage at the gate of the feedback transistor at a substantially constant value. | ¶35 | col. 2:25-29 |
| a first current supply circuit constructed to supply to a second current path a first current that is substantially constant | The regulators allegedly comprise a first current supply circuit (e.g., a diode connected transistor coupled to a second transistor) that supplies a substantially constant first current. | ¶36 | col. 2:30-32 |
| a second current supply circuit...constructed to supply a second current to said second current path with a magnitude based on said voltage at said gate of said feedback transistor and a voltage at said output of said voltage regulator circuit | The regulators allegedly comprise a second current supply circuit whose output current magnitude is based on the voltage at the feedback transistor's gate and the regulator's output voltage. | ¶37 | col. 2:32-39 |
| a pass device including a gate coupled to said second current path and adapted to receive a signal based on said current of said second current path and supply a load current to said load... | The regulators allegedly include a pass device (e.g., a transistor) whose gate is adjusted by a signal based on the current in the second current path, which in turn supplies the output load current. | ¶38 | col. 2:40-46 |
- Identified Points of Contention:
- Technical Questions: The complaint’s allegations regarding the internal operation of the voltage regulator are made "on information and belief." A central technical question will be whether discovery confirms that the accused regulator’s second current supply circuit actually functions based on the two specific inputs required by the claim (the feedback transistor gate voltage and the regulator output voltage).
- Scope Questions: The term "substantially constant" appears multiple times in the claim. The parties’ dispute may center on the degree of variation permissible for a voltage or current to be considered "substantially constant" within the context of the patent.
’838 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| In a data storage device that includes a memory having a three-dimensional (3D) memory configuration and including a structure extending through multiple layers of the memory | The accused products (e.g., Micron 7450) are data storage devices containing a 3D memory configuration with structures extending through multiple layers. | ¶52 | col. 1:41-45 |
| storing information at the data storage device, the information identifying a location associated with a variation of the structure | The accused products allegedly store information that identifies a location associated with a structural variation to compensate for cell characteristics' variability across the pillar. | ¶53 | col. 2:10-15 |
| accessing the information | The accused products allegedly access this stored information to determine finely tuned programming voltages. | ¶54 | col. 2:42-45 |
- Identified Points of Contention:
- Evidentiary Questions: The claim requires the explicit step of "storing information...identifying a location." The complaint cites a technical paper discussing "fine tuning of the programming voltage compensating cell characteristics' variability" (Compl. ¶53). A key evidentiary question will be whether this compensation scheme in the accused product actually involves storing and accessing information that "identifies a location," or if it uses a different method of compensation that does not meet this claim limitation.
- Scope Questions: The interpretation of "information identifying a location" will be critical. The question may arise whether this requires a specific address or coordinate of the variation, or if a set of corrective parameters that indirectly accounts for the variation’s effects would suffice to meet the limitation.
V. Key Claim Terms for Construction
For the ’962 Patent
- The Term: "a second current supply circuit...constructed to supply a second current...with a magnitude based on said voltage at said gate of said feedback transistor and a voltage at said output of said voltage regulator circuit" (Claim 1)
- Context and Importance: This limitation defines the core functional mechanism of the invention. The infringement analysis will likely depend on whether the accused product's circuit determines its current based on these two specific voltage inputs, as opposed to other inputs or a different control logic.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim language itself describes the relationship functionally ("based on") rather than structurally, which may support an interpretation that covers any circuit where these two voltages are inputs to the current-determining function, regardless of the specific implementation.
- Evidence for a Narrower Interpretation: The specification’s detailed description of an embodiment in Figure 3 shows a variable current source (340) with two specific reference signal inputs (341, 342) corresponding to the gate voltage and the output voltage, respectively. An argument could be made that the claim should be construed in light of this specific disclosed embodiment (’962 Patent, col. 6:45-54, Fig. 3).
For the ’838 Patent
- The Term: "storing information...identifying a location associated with a variation of the structure" (Claim 1)
- Context and Importance: This is a crucial step of the claimed method. Infringement requires more than just detecting or compensating for a variation; it requires the affirmative act of storing data that points to the variation's location. Practitioners may focus on this term because it distinguishes the invention from generalized compensation schemes.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The abstract states the method "includes storing information... The information identifies a location associated with a variation." This broad language could support an argument that any stored data which allows the controller to differentiate between cells affected and unaffected by the variation meets the limitation.
- Evidence for a Narrower Interpretation: The summary of the invention describes determining "a location of the variation of the structure" which may correspond to where "tapering' of the structure begins" (’838 Patent, col. 2:11-14). Figure 6 depicts a table mapping block numbers to specific "Location of Variation" (e.g., "WL_k"), suggesting the "information" is a specific coordinate or layer identifier. This may support a narrower construction requiring a stored physical location identifier.
VI. Other Allegations
Indirect Infringement
- For the ’962, ’051, ’314, and ’974 patents, the complaint alleges post-suit inducement of infringement, based on knowledge of the patents from the service of the original complaint. The alleged acts include inducing subsidiaries and customers through the provision of datasheets, manuals, and technical support (Compl. ¶¶41-42, 74-75, 90-91, 102-103).
- For the ’838 patent, the complaint alleges pre-suit knowledge and inducement. It alleges Defendant knew of the patent as early as June 7, 2017, from a USPTO examiner’s citation of the ’838 patent against Defendant’s own patent application, and from the patent’s appearance on the face of an issued patent assigned to Defendant (Compl. ¶56).
Willful Infringement
- The complaint alleges willful infringement for all asserted patents. For the ’838 patent, the basis is the alleged pre-suit knowledge from prosecution history events (Compl. ¶57). For the other four patents, the basis is alleged continued infringement after receiving notice of the patents via this lawsuit (Compl. ¶¶43, 76, 92, 104).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of functional operation: For the ’962 patent, does the accused voltage regulator operate according to the specific two-input control logic required by Claim 1, or does it achieve a stable voltage through a technically distinct mechanism?
- A key evidentiary question will be one of implementation: For the ’838 method patent, what evidence will show that Defendant's 3D NAND products perform the claimed steps of "storing" and "accessing" information that explicitly "identifies a location" of a structural variation, as distinguished from a more generalized scheme that compensates for performance variability without storing a location identifier?
- A central dispute may concern willfulness: Given the specific allegation that the ’838 patent was cited by the USPTO against Defendant’s own patent application years before this lawsuit, a significant question for the court will be whether Defendant’s conduct following this notice constitutes willful infringement, potentially exposing it to enhanced damages.