DCT

7:24-cv-00296

Polaris Innovations Ltd v. Qualcomm Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 7:24-cv-00296, W.D. Tex., 11/19/2024
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant Qualcomm maintains at least two regular and established places of business in Austin, Texas, and has engaged in infringing activities within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s Snapdragon processors and platforms, which incorporate certain types of semiconductor memory, infringe four patents related to memory architecture, testing, operation, and error correction.
  • Technical Context: The patents relate to fundamental aspects of high-performance semiconductor memory (DRAM), including methods for testing memory chips, managing signal timing, packaging multiple chips, and correcting data errors, technologies central to modern mobile and computing devices.
  • Key Procedural History: Plaintiff states it sent letters to Defendant regarding the alleged infringement on October 13, 2015, and again with claim charts on August 9, 2024, prior to filing the complaint. Notably, an Inter Partes Review (IPR) certificate for U.S. Patent No. 8,161,344, issued on September 26, 2019, indicates that independent claim 1 was cancelled. The complaint asserts dependent claim 7 of the ’344 Patent, which depends from the cancelled claim 1, raising a question as to its validity.

Case Timeline

Date Event
2004-10-21 U.S. Patent 7,184,339 – Priority Date
2004-11-26 U.S. Patent 7,499,371 – Priority Date
2007-02-27 U.S. Patent 7,184,339 – Issue Date
2008-03-11 U.S. Patent 8,161,344 – Priority Date
2008-09-17 U.S. Patent 7,872,936 – Priority Date
2009-03-03 U.S. Patent 7,499,371 – Issue Date
2011-01-18 U.S. Patent 7,872,936 – Issue Date
2012-04-17 U.S. Patent 8,161,344 – Issue Date
2015-10-13 Plaintiff allegedly sent first notification letter to Defendant
2019-09-26 U.S. Patent 8,161,344 – IPR Certificate issued cancelling Claim 1
2024-08-09 Plaintiff allegedly sent second notification letter with claim charts
2024-11-19 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,184,339 - “Semi-conductor component, as well as a process for the in-or output of test data,” issued February 27, 2007 (’339 Patent)

The Invention Explained

  • Problem Addressed: The patent describes the challenge of testing semiconductor memory components, particularly within "buffered memory modules." In such systems, standard read/write commands are processed by a buffer, which may not support the proprietary control signals needed to access special on-chip test registers where manufacturing test results are stored (’339 Patent, col. 3:6-18).
  • The Patented Solution: The invention provides a process where the semiconductor component can be switched from a "normal mode" (accessing the main memory array) to a "test mode." In this test mode, the address space of the test data registers is "mapped" into the address space of the main memory array. This allows a standard testing device to use conventional address and read/write commands to access the test registers, bypassing the need for special, unsupported control signals (’339 Patent, Abstract; col. 4:39-51; Fig. 4).
  • Technical Importance: This approach aimed to simplify and standardize the testing of memory chips, especially complex buffered modules, by allowing test equipment to use the same protocols for accessing both normal memory and special test registers (’339 Patent, col. 10:1-17).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1.
  • Essential elements of Claim 1 (a process) include:
    • Applying a control signal to a semi-conductor component to switch it from a first operating mode to a second operating mode.
    • Applying an address signal to the component.
    • Whereby in the second mode, one or more test data and/or operating control data registers are addressed by the address signal.
    • Whereby in the first mode, one or more useful data memory cells are addressed by the address signal.
  • The complaint reserves the right to assert additional claims (Compl. ¶31, n.5).

U.S. Patent No. 7,499,371 - “Semiconductor memory system with a variable and settable preamble,” issued March 3, 2009 (’371 Patent)

The Invention Explained

  • Problem Addressed: In high-frequency memory systems, a "preamble" is needed for the data clock signal. This preamble is a delay that allows a standing wave on the data clock line to settle, ensuring accurate data latching. The patent notes that a fixed preamble is inefficient, as higher frequencies require longer preambles for accuracy, while lower frequencies can operate reliably with shorter preambles, making a fixed-length preamble a source of unnecessary latency at lower speeds (’371 Patent, col. 1:47-65).
  • The Patented Solution: The patent discloses a memory system where the preamble—defined as the number of clock cycles between the first edge of the data clock signal and the first bit of the data signal—is variable and can be configured. This setting can be accomplished via a configuration instruction, such as a Mode Register Set (MRS) command, allowing the system to optimize the preamble length for the current operating frequency (’371 Patent, Abstract; col. 2:5-17).
  • Technical Importance: This invention provides a method to dynamically balance performance (shorter latency) and signal integrity (reliable data capture) across a range of operating frequencies in advanced memory systems (’371 Patent, col. 2:55-60).

Key Claims at a Glance

  • The complaint asserts at least independent claim 6.
  • Essential elements of Claim 6 (a system) include:
    • A semiconductor memory apparatus.
    • A processor unit configured to:
      • transmit a command instruction (e.g., write/read) to the memory apparatus;
      • communicate a data signal with the memory apparatus;
      • transmit a data clock signal to latch the data signal; and
      • set a preamble, defined as the time between the first edge of the data clock signal and the first bit of the data signal.
    • The data clock signal is present only during a read or write operation.
    • The preamble is set by setting a number of clock cycles of the data clock signal.
  • The complaint reserves the right to assert additional claims (Compl. ¶52).

Multi-Patent Capsule: U.S. Patent No. 7,872,936 - “System and method for packaged memory,” issued January 18, 2011 (’936 Patent)

  • Technology Synopsis: The patent describes a multi-chip memory device that integrates one or more memory die with a separate memory controller and interface die into a single, stacked package (’936 Patent, Abstract). This architecture aims to reduce the size, power, and cost of memory systems by replacing multiple discrete components with a single, highly integrated packaged solution (’936 Patent, col. 1:40-44).
  • Asserted Claims: The complaint asserts at least independent claim 1 (Compl. ¶70).
  • Accused Features: The complaint alleges that Qualcomm's Snapdragon products incorporating "MCeP-based stack of AP [Application Processor] and LPDDR4X/5/5X memory" infringe the ’936 Patent (Compl. ¶68).

Multi-Patent Capsule: U.S. Patent No. 8,161,344 - “Circuits and methods for error coding data blocks,” issued April 17, 2012 (’344 Patent)

  • Technology Synopsis: The patent discloses a circuit with at least two selectable error coding paths for creating an error-coded data block. One path includes a "data arrangement alteration device" that reorders the data before coding, while the other path may not. A control indicator selects which path to use, allowing the system to flexibly apply different error coding strategies optimized for different types of data errors (e.g., temporal vs. spatial burst errors) (’344 Patent, Abstract; col. 2:35-43).
  • Asserted Claims: The complaint asserts at least claim 7, which depends from claim 1 (Compl. ¶87).
  • Accused Features: The complaint alleges that the error correction (ECC) and Data Bus Inversion (DBI) features in Snapdragon products that use LPDDR5X memory infringe the ’344 Patent. The ability to enable or disable these features is alleged to correspond to the selection between different error coding paths (Compl. ¶¶89-91).

III. The Accused Instrumentality

Product Identification

  • The complaint names Qualcomm's Snapdragon 4, 6, 7, 8, and X Series processors and platforms as the "Accused Instrumentalities" (Compl. ¶10). The infringement allegations are tied to processors that incorporate specific memory technologies, namely LPDDR4/4X and LPDDR5/5X SDRAM (Compl. ¶¶29, 50, 68, 85).

Functionality and Market Context

  • The Accused Instrumentalities are System-on-Chip (SoC) processors that form the core of numerous mobile devices. The complaint focuses on their interaction with industry-standard memory. For example, it alleges that the processors issue commands defined by JEDEC standards, such as "Mode Register Write" commands, to configure and operate the memory (Compl. ¶¶34, 38). A device specification for the Qualcomm SM8250 processor is referenced, highlighting its use of "Quad-channel package-on-package (PoP) high-speed LPDDR5/LPDDR4X SDRAM" (Compl. ¶33). The complaint alleges these products are central to Qualcomm's semiconductor business (Compl. ¶5). The complaint includes a high-level block diagram of the SM8450, showing a "PoP memory" block connected to the core processor functions (Compl. ¶55; p. 22).

IV. Analysis of Infringement Allegations

’339 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
[a] process for inputting and/or outputting test data and/or semi-conductor component operating control data into or from a semi-conductor component... The accused Snapdragon processors perform processes for inputting/outputting data to/from the associated LPDDR memory. ¶33 col. 11:13-22
applying a control signal to the semi-conductor component for switching over the semi-conductor component from a first to a second operating mode; The memory controller issues a "Mode Register Write-1" (MRW-1) command, which allegedly causes the memory to switch from a first mode (memory array access) to a second mode (mode register access). ¶¶34-35 col. 10:15-24
applying an address signal to the semi-conductor component, The memory controller applies address signals on the command/address (CA) pins (e.g., CA0-CA6) to specify a target register. ¶¶36-37 col. 10:43-50
whereby in the second operating mode one or more of the test data and/or semi-conductor component operating control data registers of the semi-conductor component is addressed by the address signal, In the alleged "second operating mode" following an MRW-1 command, a subsequent "Mode Register Write-2" command uses the address signal to write data to a specific Mode Register (e.g., for DQ Calibration), which is alleged to be a "test data" or "operating control data" register. ¶¶38-39 col. 10:43-50
and in the first operating mode one or more of the useful data memory cells. In the "first operating mode," standard write commands (e.g., WR16) use address signals to access the main memory array (useful data cells). ¶39 col. 9:4-14

The complaint includes a JEDEC command truth table to show that a "Mode Register Write-1" command is distinct from a standard "WRITE" command. (Compl. ¶34; p. 12).

  • Identified Points of Contention:
    • Scope Questions: A central question will be whether a standard "Mode Register" used for runtime configuration (e.g., calibration, timing settings) in a commercial product constitutes a "test data and/or semi-conductor component operating control data register" as contemplated by the patent. The patent specification appears to frame these registers in the context of storing results from manufacturing tests (’339 Patent, col. 2:60-65).
    • Technical Questions: The analysis will question whether issuing a standard JEDEC "MRW-1" command constitutes "switching over the semi-conductor component from a first to a second operating mode" in the specialized sense described by the patent, versus simply performing a standard configuration operation available in normal operation.

’371 Patent Infringement Allegations

Claim Element (from Independent Claim 6) Alleged Infringing Functionality Complaint Citation Patent Citation
a semiconductor memory apparatus; The SM8450 processor is part of a Package-on-Package (PoP) system that includes a "companion memory device" such as LPDDR5 SDRAM. ¶54 col. 3:26-30
a processor unit which is configured to: transmit a command instruction... wherein the command instruction is at least one of a write instruction and a read instruction; The SM8450 contains a "Processors" block that transmits command instructions (e.g., WRITE commands) to the memory apparatus. ¶55 col. 3:27-33
communicate a data signal with the semiconductor memory apparatus; The SM8450 is configured to communicate data signals via its data pins (e.g., EBIO_DQ_0). ¶56 col. 4:1-3
transmit a data clock signal to latch the data signal; The SM8450 is configured to transmit a data clock signal (WCK) to the memory apparatus. ¶56 col. 4:3-4
set a preamble, wherein the preamble is a period of time between a first edge of the data clock signal and a first bit of the data signal... The processor unit sets a preamble, illustrated in a JEDEC timing diagram as the "tWCKPRE_Static" or "tWCKPRE_Toggle_WR" period. ¶57 col. 4:31-35
wherein the data clock signal is present only during a read or write operation... The JEDEC timing diagram shows the data clock (WCK_t/c) is only active during the write operation, initiated by the command. ¶58 col. 4:55-61
wherein the preamble is set by setting a number of clock cycles of the data clock signal... JEDEC standard tables specify preamble-related parameters (e.g., "tWCKPRE_Static") in terms of a number of clock cycles ("nCK"). ¶59 col. 4:9-12

The complaint provides a JEDEC timing diagram, Figure 71, to illustrate the preamble period during a write command. (Compl. ¶57; p. 26).

  • Identified Points of Contention:
    • Scope Questions: The claim requires the "processor unit" to be configured to "set a preamble." A potential dispute is whether the Qualcomm processor performs this action itself, or if it merely sends a standard configuration value (e.g., via an MRS command) to the memory device, which then internally sets its own preamble based on that value. The locus of the "setting" action will be a key issue.
    • Technical Questions: Does the functionality described in the JEDEC standard, which the accused products implement, map directly onto the specific configuration method claimed by the patent, or are there technical differences in how the preamble is established and controlled?

V. Key Claim Terms for Construction

For the ’339 Patent

  • The Term: "test data and/or semi-conductor component operating control data registers" (Claim 1)
  • Context and Importance: The viability of the infringement claim hinges on whether standard Mode Registers (MRs) in LPDDR memory, which are used to configure operational parameters like DQ calibration, fall within this definition. Qualcomm may argue these are routine operational registers, while Polaris will likely argue they are a type of "operating control data register."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The term itself includes "operating control data registers," which could be argued to encompass any register that controls the component's operation, including standard Mode Registers. Claim 1 is part of a process for "inputting and/or outputting" such data, which is what happens during a Mode Register Write.
    • Evidence for a Narrower Interpretation: The patent’s background and detailed description repeatedly link these registers to "test (result) data generated during... test procedures" related to manufacturing (’339 Patent, col. 2:60-65; col. 7:21-24). The patent’s solution is aimed at accessing these registers when they are otherwise inaccessible via standard protocols, a situation that may not apply to the accused products' standard Mode Registers.

For the ’371 Patent

  • The Term: "processor unit which is configured to... set a preamble" (Claim 6)
  • Context and Importance: Infringement requires that the accused processor unit performs the action of "setting" the preamble. Practitioners may focus on this term because the evidence shows the processor sends a command based on a JEDEC standard, and the defense may argue that the memory device itself, not the processor, performs the actual "setting" in response to that command. The claim language assigns the configuration action to the processor unit.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim states the processor unit is "configured to... set a preamble." One could argue that being configured to send the specific command that causes the preamble to be set is equivalent to being configured to set it. The specification states the system is "configurable so that the preamble... can be set" (’371 Patent, col. 2:35-37).
    • Evidence for a Narrower Interpretation: The claim recites a list of actions the processor is configured to perform (transmit, communicate, set). A narrow reading would require the processor to be the active agent in the setting process, not merely an initiator that delegates the setting function to the memory apparatus. The specification describes setting the preamble "using a configuration instruction" (’371 Patent, col. 2:6-7), which could be interpreted as the instruction itself being the mechanism, with the processor merely as the messenger.

VI. Other Allegations

  • Indirect Infringement: For all asserted patents, the complaint alleges induced infringement. It claims Qualcomm knowingly and intentionally induces infringement by providing customers with advertisements, datasheets, and other instructional materials that promote the use of the accused products in an infringing manner (Compl. ¶¶42-43, 60-61, 77-78, 93-94).
  • Willful Infringement: Willfulness is alleged for all asserted patents. The claim is based on alleged pre-suit knowledge of the patents and infringement, citing notification letters sent to Qualcomm on October 13, 2015, and August 9, 2024 (Compl. ¶¶23, 44, 62, 79, 95).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. A core issue will be one of definitional scope: Can standard, operational "Mode Registers" in commercial memory, governed by JEDEC standards, be construed as the specialized "test data registers" described in the ’339 Patent, which the specification ties to manufacturing-line testing?
  2. A second key issue will be one of invalidity: The complaint asserts claim 7 of the ’344 Patent, which is dependent on claim 1. Given that an IPR certificate indicates claim 1 was cancelled prior to the filing of the suit, a threshold question is whether the assertion of claim 7 is legally viable.
  3. A third central question will be one of functional attribution: For the ’371 Patent, does the accused processor "set" the preamble as required by the claim, or does it merely transmit a standard command that instructs the separate memory apparatus to perform the setting function? The case may turn on whether instructing an action is legally equivalent to performing it under the claim's language.