InnoMemory LLC v. BOXX Tech LLC

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: BOXX Technologies LLC (Delaware)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 7:25-cv-42, W.D. Tex., 02/02/2025
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant maintains an established place of business in the district and has committed acts of patent infringement there.
• Core Dispute: Plaintiff alleges that certain Defendant products infringe a patent related to methods for reducing power consumption in memory devices during refresh operations.
• Technical Context: The technology concerns power-saving techniques for dynamic random-access memory (DRAM), which is critical for extending battery life in portable electronics and reducing energy use in high-performance computing systems.
• Key Procedural History: The complaint does not mention any prior litigation, inter partes review (IPR) proceedings, or specific licensing history related to the patent-in-suit. The patent-in-suit is a continuation of a prior application.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

• Issued: June 6, 2006

The Invention Explained

• Problem Addressed: The patent describes a problem in conventional dynamic semiconductor memory devices, particularly for battery-powered applications. Even in a low-power standby mode, these devices consume significant current by refreshing all memory cells, regardless of whether the data in every cell needs to be retained ('960 Patent, col. 1:35-56). Conventional methods that refresh the entire memory array activate periphery circuits for all sections, even when only a portion of the memory is being refreshed, leading to unnecessary power consumption ('960 Patent, col. 2:25-29).
• The Patented Solution: The invention proposes a method and architecture to reduce power consumption by selectively controlling background operations, such as refresh cycles, on a section-by-section basis within the memory array ('960 Patent, Abstract). The system generates control signals based on a programmable address signal, which dictates which memory sections should be active. These control signals are then presented only to the periphery array circuits of the targeted sections, leaving the circuits for other sections disabled and inactive to save power ('960 Patent, col. 2:36-44; Fig. 3). This allows for partial-array refresh without energizing the entire device's support circuitry.
• Technical Importance: The approach provides a way to significantly lower standby power consumption in memory devices, which was increasingly important for the growing market of mobile and battery-operated terminals ('960 Patent, col. 1:32-35).

Key Claims at a Glance

• The complaint alleges infringement of "one or more claims" but does not specify which ones (Compl. ¶11). Independent claim 1 is representative of the method claims.
• The essential elements of independent claim 1 include:
  • controlling background operations in each of a plurality of sections of a memory array in response to one or more control signals;
  • wherein the control signals are generated in response to a programmable address signal;
  • wherein the background operations can be enabled simultaneously in two or more sections independently of any other section; and
  • presenting the control signals and decoded address signals to one or more periphery array circuits of the plurality of sections.
• The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

• The complaint does not identify any specific accused products by name. It refers generally to "Exemplary Defendant Products" that are purportedly identified in an exhibit attached to the complaint (Compl. ¶11, ¶13).

Functionality and Market Context

• The complaint does not describe the specific functionality or features of the accused products. It alleges that Defendant's employees "internally test and use these Exemplary Products" (Compl. ¶12). The complaint does not provide any allegations regarding the products' commercial importance or market position.

IV. Analysis of Infringement Allegations

The complaint’s infringement allegations are made by reference to claim charts in "Exhibit 2," which was not included in the provided filing (Compl. ¶13-14). The complaint states that these charts show that the "Exemplary Defendant Products practice the technology claimed" and "satisfy all elements of the Exemplary '960 Patent Claims" (Compl. ¶13). Without this exhibit, a detailed element-by-element analysis is not possible based on the complaint alone. The document alleges direct infringement by Defendant for making, using, offering to sell, selling, and/or importing the accused products (Compl. ¶11).

No probative visual evidence provided in complaint.

V. Key Claim Terms for Construction

• The Term: "background operations"

  • Context and Importance: This term defines the scope of the activities to which the power-saving method applies. The infringement analysis will depend on whether the accused devices perform operations that fall within the patent's definition of "background operations." Practitioners may focus on this term because its breadth is a central feature of the claim.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification suggests the term is not limited to a single function, stating that the invention reduces power "during background operations, such as memory cell refresh operations" ('960 Patent, col. 2:47-49). It further notes the invention may "perform parity checking and/or housekeeping operations on one or more sections of a memory array" ('960 Patent, col. 2:53-55; Claim 4).
    • Evidence for a Narrower Interpretation: A defendant could argue the term's meaning is principally defined by the patent's primary focus. The title, abstract, and background are all heavily focused on "refresh operations," which could suggest that other "background operations" must be analogous to memory refresh ('960 Patent, Title; Abstract; col. 1:12-14).

• The Term: "programmable address signal"

  • Context and Importance: This term is the input that controls which memory sections are refreshed. The mechanism by which an address signal is deemed "programmable" will be critical to determining infringement, as it distinguishes the invention from systems with fixed or non-selective refresh schemes.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: Claim 1 requires only that the control signals be "generated in response to a programmable address signal," without specifying how that signal is programmed. This could be read to cover any system where the selection of memory sections for background operations can be modified or set.
    • Evidence for a Narrower Interpretation: The specification describes a specific embodiment where this programmability is achieved by storing a "block address" in a "refresh address register" (138), which is then used to generate control signals (REF0-REFn) that enable or disable periphery circuits for corresponding memory sections ('960 Patent, col. 8:1-4; Fig. 3). A defendant might argue that "programmable" requires a dedicated, loadable register as shown in the preferred embodiment.

VI. Other Allegations

• Indirect Infringement: The complaint does not contain specific factual allegations to support claims of induced or contributory infringement.
• Willful Infringement: The complaint does not allege pre- or post-suit knowledge of the patent or any facts that would support a claim of willful infringement. However, the prayer for relief requests a judgment that the case be declared "exceptional within the meaning of 35 U.S.C. § 285" (Compl. p. 4, ¶E.i).

VII. Analyst’s Conclusion: Key Questions for the Case

1. A primary evidentiary question will be one of technical specificity: given the complaint's conclusory allegations and reliance on an unattached exhibit, what specific hardware architecture and operational modes of the accused BOXX products are alleged to perform the selective, section-based power-saving functions recited in the claims?
2. A core issue will be one of definitional scope: can the term "background operations," which the patent illustrates with memory refresh and parity checking, be construed to cover other power-management or low-activity states implemented in modern high-performance computing memory systems?
3. A key infringement question will be one of independent control: does the accused technology allow memory sections to be enabled "independently of any other section" as required by claim 1, or do the accused systems employ a more interdependent or hierarchical control scheme that falls outside the claim's scope?