InnoMemory LLC v. First National Bank Of Bastrop

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: First National Bank of Bastrop (Texas)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 7:25-cv-00043, W.D. Tex., 02/02/2025
• Venue Allegations: Venue is alleged to be proper in the Western District of Texas because the Defendant maintains an established place of business in the District.
• Core Dispute: Plaintiff alleges that Defendant’s use of certain unidentified products infringes a patent related to methods for reducing power consumption in memory devices during refresh operations.
• Technical Context: The technology concerns power-saving techniques for dynamic random-access memory (DRAM), a critical component in most computing devices, by selectively refreshing only portions of the memory array.
• Key Procedural History: The complaint does not mention any prior litigation, inter partes review proceedings, or licensing history related to the patent-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

• Patent Identification: U.S. Patent No. 7,057,960, "Method and architecture for reducing the power consumption for memory devices in refresh operations," issued June 6, 2006.

U.S. Patent No. 7,057,960 - "Method and architecture for reducing the power consumption for memory devices in refresh operations"

The Invention Explained

• Problem Addressed: The patent addresses the problem of high power consumption in conventional dynamic random access memories (DRAMs) during standby mode (’960 Patent, col. 1:30-34). Specifically, it notes that conventional methods activate the support circuitry (periphery array circuits) for all sections of a memory array even when only a portion of the array requires refreshing, leading to inefficient power use, which is a significant issue for battery-powered devices ('960 Patent, col. 2:26-34).
• The Patented Solution: The invention proposes a method and architecture to reduce power consumption by enabling refresh operations for only specific, selected sections of a memory array ('960 Patent, col. 2:47-49). The core of the solution is to control the background operations (e.g., refresh) in one or more memory sections via control signals, while leaving the support circuits for the other, non-refreshed sections inactive ('960 Patent, Abstract; col. 2:51-53). A programmable address signal, stored in a register, determines which sections are to be refreshed ('960 Patent, col. 11:1-4).
• Technical Importance: This approach allows for a "partial array refresh," which can significantly reduce standby current, a critical factor for extending the battery life of mobile and portable electronic devices ('960 Patent, col. 1:35-48).

Key Claims at a Glance

The complaint refers to "Exemplary '960 Patent Claims" but does not identify specific claims in the body of the complaint (Compl. ¶11). Claim 1 is the first independent method claim.

• Independent Claim 1:
  • A method for reducing power consumption during background operations in a memory array with a plurality of sections, comprising the steps of:
  • controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals, wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
  • presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.

III. The Accused Instrumentality

Product Identification

• The complaint does not name any specific accused product, method, or service. It refers generally to "Defendant products" and "Exemplary Defendant Products" that are purportedly identified in an "Exhibit 2" attached to the complaint (Compl. ¶¶11, 13). This exhibit was not provided.

Functionality and Market Context

• The complaint alleges that the "Exemplary Defendant Products practice the technology claimed by the '960 Patent" (Compl. ¶13). Given that the Defendant is a bank, these products are presumably computer systems, servers, or other standard hardware containing memory chips that allegedly perform the patented power-saving methods (Compl. ¶3). The complaint makes no allegations regarding the products' specific commercial importance beyond their use by the Defendant in its business activities (Compl. ¶6). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint alleges that infringement is detailed in claim charts in an Exhibit 2, which is incorporated by reference but was not provided with the complaint (Compl. ¶¶13-14). The complaint's narrative asserts that the "Exemplary Defendant Products incorporated in these charts satisfy all elements of the Exemplary '960 Patent Claims" (Compl. ¶13). Without the exhibit, a detailed element-by-element analysis is not possible.

• Identified Points of Contention:
  • Technical Questions: A primary question will be whether the memory devices used by the Defendant actually perform the claimed method. Specifically, what evidence can the Plaintiff provide that the accused memory chips not only perform a partial refresh, but do so by selectively deactivating the "periphery array circuits" of non-refreshed sections, as required by the patent's teachings and claims? Proving the internal operation of commodity hardware components may present an evidentiary challenge.
  • Scope Questions: The case may raise questions about the scope of "use" infringement by an end-user. The Defendant, a bank, is not alleged to manufacture or design memory chips. The dispute will likely focus on whether the ordinary operation of its computer systems constitutes "using" the patented method, particularly if the allegedly infringing functionality is a low-level, automatic feature of a standard component.

V. Key Claim Terms for Construction

• The Term: "background operations"

• Context and Importance: This term defines the scope of activities to which the power-saving method applies. The complaint’s theory rests on this term covering the refresh operations in the accused products. Practitioners may focus on this term to determine if it is limited to the specific examples in the patent or can cover a wider range of internal memory management functions.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The claims themselves are not explicitly limited to refresh. The specification states that background operations can include "parity checking and/or housekeeping operations" in addition to refresh, suggesting the term is not narrowly restricted to a single function ('960 Patent, col. 2:53-55).
  • Evidence for a Narrower Interpretation: The patent's title, abstract, and background are overwhelmingly focused on "refresh operations" as the context for the invention, which a party could argue cabins the meaning of the more general term "background operations" used in the claims ('960 Patent, Title; Abstract; col. 1:12-14).

• The Term: "programmable address signal"

• Context and Importance: This signal is the input that dictates which memory sections will have their background operations enabled. The infringement analysis will depend on whether the control mechanism in the accused products meets this "programmable" requirement.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The term is not narrowly defined. A party might argue that any signal that can be set or altered (e.g., through a mode register setting in a standard DRAM) to select a partial-refresh mode qualifies as "programmable."
  • Evidence for a Narrower Interpretation: The specification describes this signal as a "block address" stored in a dedicated "refresh address register," which is loaded with the portion of the memory to be refreshed ('960 Patent, col. 2:63-65; col. 8:1-4). This could support an argument that the term requires a specific, address-based programming mechanism, not just a simple mode-select bit.

• The Term: "periphery array circuits"

• Context and Importance: The invention's power-saving benefit comes from deactivating these specific circuits. Infringement requires showing that the accused devices have corresponding circuits and that they are selectively disabled. The definition of this term is therefore central to the technical infringement analysis.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The term is a general structural one. A party could argue it broadly covers any support circuitry located at the periphery of a memory cell array that is involved in accessing the cells.
  • Evidence for a Narrower Interpretation: Dependent claim 5 provides a specific definition, stating that "periphery array circuits" comprise "one or more circuits from the group consisting of sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits" ('960 Patent, col. 12:1-4). An argument could be made, via the doctrine of claim differentiation or by importing limitations, that this specific list informs the proper construction of the term.

VI. Other Allegations

• Indirect Infringement: The complaint does not allege any facts that would support a claim for either induced or contributory infringement.
• Willful Infringement: The complaint does not use the word "willful." However, in the prayer for relief, it requests that the case be declared "exceptional within the meaning of 35 U.S.C. § 285" and seeks an award of attorneys' fees (Compl. ¶E.i). Such a request is typically predicated on allegations of willful infringement or other forms of egregious litigation conduct. The complaint does not plead any facts regarding pre- or post-suit knowledge by the Defendant.

VII. Analyst’s Conclusion: Key Questions for the Case

1. Evidentiary Proof: A central issue will be evidentiary. Given the lack of detail in the complaint and the nature of the defendant as an end-user, a key question is what factual basis the plaintiff has for alleging that the internal, micro-level operations of commodity memory chips used by the bank meet the specific limitations of the claims, particularly the selective deactivation of "periphery array circuits".

2. Claim Scope and End-User Liability: The case may turn on a question of claim scope as applied to an end-user. Can the "programmable address signal" limitation be met by the standard operation of off-the-shelf memory controllers and DRAM modules, or does it require a more specific, user-directed programming capability that would not be present in the defendant's systems? This raises the broader legal question of the extent to which operating standard equipment constitutes "use" of a patented method that is deeply embedded within a component.

3. Basis for "Exceptional Case" Allegation: The complaint requests a finding that the case is exceptional under 35 U.S.C. § 285 but pleads no supporting facts, such as pre-suit knowledge or willful conduct. A key procedural question will be whether this bare-bones allegation can survive a motion to dismiss, and what facts, if any, will be developed in discovery to substantiate it.