InnoMemory LLC v. Southstar Bank SSB

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory, LLC (Texas)
  • Defendant: Southstar Bank S.S.B. (Texas)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 7:25-cv-00049, W.D. Tex., 02/03/2025
• Venue Allegations: Plaintiff alleges venue is proper because Defendant has an established place of business in the district, has committed acts of patent infringement in the district, and Plaintiff has suffered harm there.
• Core Dispute: Plaintiff alleges that unspecified products used by Defendant infringe a patent related to methods for reducing power consumption in memory devices during refresh operations.
• Technical Context: The lawsuit concerns the field of dynamic random-access memory (DRAM), specifically the power-saving techniques used during standby modes in electronic devices.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patent-in-suit.

Case Timeline

Date	Event
2002-03-04	Earliest Priority Date Claimed by U.S. Patent No. 7,057,960 (from parent application 10/090,850)
2003-07-29	Application Date for U.S. Patent No. 7,057,960
2006-06-06	Issue Date for U.S. Patent No. 7,057,960
2025-02-03	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,057,960 - Method and architecture for reducing the power consumption for memory devices in refresh operations

• Patent Identification: U.S. Patent No. 7,057,960, issued June 6, 2006.

The Invention Explained

• Problem Addressed: Conventional dynamic semiconductor memory devices are configured to refresh all memory cells during standby mode, which consumes significant power even if only a portion of the memory contains data that needs to be retained. This is particularly problematic for battery-powered portable devices where standby time is critical (’960 Patent, col. 1:49-56). Another disadvantage noted is that conventional partial-refresh methods still activate the periphery array circuits for all memory quadrants, consuming unnecessary power (’960 Patent, col. 2:25-28).
• The Patented Solution: The invention proposes a method and architecture where a memory array is divided into multiple sections (e.g., quadrants), and the background "refresh" operations can be controlled for each section independently (’960 Patent, col. 2:36-44). By using specific control signals generated in response to a programmable address, the system can activate the power-consuming "periphery array circuits" only for the sections being refreshed, while leaving the circuits for other sections inactive (’960 Patent, col. 2:50-55). Figure 3 illustrates this concept, showing a memory array (104) divided into four quadrants (124a-d), each capable of being independently controlled by distinct refresh signals (REF0-REF3) from the array control circuit (146).
• Technical Importance: This approach allows for a more granular control over power consumption in DRAM, enabling significant power savings in devices that only require a small fraction of their memory to be active during standby, a key consideration for the growing mobile device market at the time (’960 Patent, col. 1:36-48).

Key Claims at a Glance

• The complaint asserts "one or more claims" without specifying them, instead referring to an unprovided exhibit (Compl. ¶¶ 11, 13). Independent claim 1 is representative of the method claims mentioned in the complaint.
• Independent Claim 1:
  • A method for reducing power consumption during background operations in a memory array with a plurality of sections, comprising the steps of:
  • controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals, wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
  • presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.
• The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

• The complaint does not identify any specific accused products, services, or methods by name. It refers generally to "Defendant products identified in the charts incorporated into this Count below" and "Exemplary Defendant Products" (Compl. ¶¶ 11, 13). The charts referenced are in an exhibit that was not filed with the complaint.

Functionality and Market Context

• The complaint provides no description of the functionality or market context of any accused instrumentality. It alleges that Defendant, a bank, has made, used, sold, or imported infringing devices, but provides no further detail (Compl. ¶11).

IV. Analysis of Infringement Allegations

The complaint alleges direct infringement of method claims of the ’960 Patent but provides no specific factual allegations mapping any feature of an accused product to the elements of any asserted claim (Compl. ¶11). Instead, the complaint states that "Exhibit 2 includes charts comparing the Exemplary '960 Patent Claims to the Exemplary Defendant Products" and that these charts demonstrate infringement (Compl. ¶13). As Exhibit 2 was not provided, a detailed analysis of the infringement allegations is not possible. The narrative theory is that the unspecified "Exemplary Defendant Products practice the technology claimed by the '960 Patent" (Compl. ¶13).

• Identified Points of Contention: Given the lack of factual detail in the complaint, any infringement dispute will first center on identifying the accused products and their mode of operation. Subsequently, based on the patent's claims, the dispute may focus on several technical and legal questions:
  • Technical Question: What evidence demonstrates that the accused memory systems can and do enable background operations (like refresh) in multiple, specific sections of a memory array while leaving other sections' periphery circuits inactive, as required by the claims?
  • Scope Question: Does the mechanism for selecting which memory sections to refresh in the accused products meet the claim limitation of being responsive to a "programmable address signal"? The interpretation of "programmable" will be critical.
  • Scope Question: Do the accused products allow background operations to be enabled in sections "independently of any other section"? A system that refreshes in fixed, non-independent groupings (e.g., all-or-nothing, or only in fixed halves) may not meet this limitation.

V. Key Claim Terms for Construction

• The Term: "programmable address signal" (from Claim 1)

• Context and Importance: This term is central to how the patented selective refresh is initiated. The infringement analysis will depend on whether the accused devices use a signal that qualifies as "programmable" to designate which memory sections to refresh. Practitioners may focus on this term to determine if a hard-wired or less flexible system falls outside the scope of the claim.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The term itself is not explicitly defined. A party might argue it should be given its plain and ordinary meaning, covering any signal that can be set or altered to designate an address, without requiring a specific type of user interface or programming method.
  • Evidence for a Narrower Interpretation: The specification describes this signal as originating from a "refresh address register" that stores a "block address" to control which portion of the array is refreshed (’960 Patent, col. 8:1-4; col. 9:61-65). A party could argue this context limits the term to a signal generated from a dedicated, loadable register, as shown in the embodiments (e.g., register 138 in FIG. 3).

• The Term: "independently of any other section" (from Claim 1)

• Context and Importance: This limitation defines the granularity of control required by the invention. The outcome of the case could turn on whether the accused systems provide this level of independent control or operate on sections in a linked or dependent manner.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The specification states the invention provides the "capability to refresh one-fourth, one-half, three-quarters, and/or all of the memory array space" (’960 Patent, col. 7:65-col. 8:1). This could support an interpretation where any combination is possible, satisfying the "independent" requirement.
  • Evidence for a Narrower Interpretation: The phrase "enabled simultaneously in two or more of said plurality of sections independently of any other section" suggests that the selection of, for example, sections 1 and 3 for refresh must not be constrained by the status of sections 2 or 4. A defendant might argue that its system, if it only allows for refreshing pre-determined blocks (e.g., sections 1&2 together, or 3&4 together), does not allow for enabling sections "independently."

VI. Other Allegations

• Indirect Infringement: The complaint does not allege indirect infringement.
• Willful Infringement: The complaint does not contain any factual allegations to support a claim for willful infringement, such as allegations of pre-suit or post-suit knowledge of the patent or infringement. The prayer for relief includes a request that the case be declared "exceptional" under 35 U.S.C. § 285, but no basis for this is provided in the pleadings (Compl. ¶E.i).

VII. Analyst’s Conclusion: Key Questions for the Case

1. A Threshold Evidentiary Question: The primary issue is the complete absence of factual specificity in the complaint. Before any technical or legal analysis can occur, the Plaintiff must identify the accused products and provide evidence of how their memory systems actually operate, a burden not met in the initial pleading which relies on an unprovided exhibit.
2. A Core Issue of Claim Scope: Assuming an accused product is identified, the case will likely turn on the construction of "programmable address signal". The key question for the court will be whether this term requires a dedicated, loadable register as shown in the patent's embodiments, or if it can be read more broadly to cover other methods of selecting memory sections for low-power operations.
3. A Key Question of Technical Functionality: The infringement analysis will hinge on whether the accused memory controllers can and do operate sections "independently of any other section." The central factual dispute will be whether the accused systems provide the granular, independent control claimed by the patent or if they refresh memory sections in fixed, dependent groups that fall outside the claim's scope.