DCT

7:25-cv-00083

Xueshan Tech Inc v. Qualcomm Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 7:25-cv-00083, W.D. Tex., 02/21/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendants maintain at least two regular and established places of business in Austin, Texas, and have committed acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s Snapdragon and other processor families infringe six patents related to memory controller calibration, data access using internal clocks, display dimming control, and video processing technologies.
  • Technical Context: The asserted patents cover fundamental technologies for system-on-a-chip (SoC) performance, including memory interface timing, dynamic display brightness adjustment, and efficient video compression, which are critical in the mobile and computing device markets.
  • Key Procedural History: The complaint alleges Plaintiff sent letters to Defendant on November 30, 2023, and February 20, 2025, identifying the asserted patents and providing exemplary infringement charts. The complaint states that on May 30, 2024, Defendant informed Plaintiff it was not interested in a license.

Case Timeline

Date Event
2009-07-06 ’846 Patent Priority Date
2009-03-18 ’089 Patent Priority Date
2009-12-29 ’946 Patent Priority Date
2010-01-13 ’211 Patent Priority Date (Filing Date)
2012-05-24 ’013 Patent Priority Date
2013-03-05 ’089 Patent Issue Date
2013-03-12 ’946 Patent Issue Date
2013-05-28 ’211 Patent Issue Date
2013-06-11 ’846 Patent Issue Date
2013-12-06 ’730 Patent Priority Date
2015-06-23 ’013 Patent Issue Date
2017-11-07 ’730 Patent Issue Date
2023-11-30 Plaintiff sends first pre-suit letter to Defendant
2024-05-30 Defendant allegedly informs Plaintiff of no interest in license
2025-02-20 Plaintiff sends second pre-suit letter to Defendant
2025-02-21 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,391,089 - “Method and circuit of calibrating data strobe signal in memory controller”

The Invention Explained

  • Problem Addressed: The patent describes the technical challenge of accurately delaying a data strobe (DQS) signal by a precise 90-degree phase shift within a memory controller, which is necessary for correctly latching data from high-speed memory (Compl. ¶37; ’089 Patent, col. 3:1-5). It notes that conventional master-slave Delay Locked Loop (DLL) circuits can suffer from inaccuracies due to mismatches between the two delay chains, a problem exacerbated by shrinking semiconductor fabrication processes (’089 Patent, col. 3:56-68).
  • The Patented Solution: The invention proposes a method using a single delay chain that is calibrated in two distinct periods. In a first period (e.g., a memory refresh cycle), the circuit determines a "delay calibrating parameter" which corresponds to the number of delay buffers required to achieve the target phase shift (’089 Patent, Fig. 8, element 810). In a second period (e.g., a data access cycle), the incoming DQS signal is passed through that specific number of serially connected buffers to apply the calibrated delay, thereby generating an accurately phase-shifted signal for data latching (’089 Patent, Abstract; Fig. 8, element 820).
  • Technical Importance: This approach seeks to improve the reliability of high-speed memory interfaces by creating a more robust DQS delay mechanism that is less susceptible to process, voltage, and temperature variations that can cause mismatches in traditional dual-chain DLLs (’089 Patent, col. 7:17-29).

Key Claims at a Glance

  • The complaint asserts independent method claim 1 and dependent claims 2, 4, 5, 7, and 8 (Compl. ¶35).
  • The essential elements of independent claim 1 are:
    • detecting a delay calibrating parameter during a first period; and
    • delaying the strobe signal by a predetermined phase according to the delay calibrating parameter during a second period.
  • The complaint reserves the right to assert additional claims (Compl. ¶35, n.5).

U.S. Patent No. 8,395,946 - “Data access apparatus and associated method for accessing data using internally generated clocks”

The Invention Explained

  • Problem Addressed: The patent addresses the limitations of conventional data receiving circuits that rely on an external data strobe signal from memory and use a complex Delay Locked Loop (DLL) to generate the proper sampling clock (’946 Patent, col. 1:50-59). Such DLLs are described as being large, power-intensive, and slow to stabilize, particularly as data transmission frequencies increase (’946 Patent, col. 2:1-12).
  • The Patented Solution: The invention discloses a data access apparatus that uses a plurality of internal, free-running clocks generated by an on-chip Phase Locked Loop (PLL) instead of relying on the external strobe signal (’946 Patent, Abstract). During a "training mode," a calibrating circuit tests the internal clocks to determine a "preferred clock" that correctly samples a known training data pattern (Compl. ¶59; ’946 Patent, Fig. 3, element 316). During "normal mode," this selected preferred clock is then used by a latching module to sample the actual data from memory (’946 Patent, Abstract).
  • Technical Importance: This design aims to create a simpler, smaller, and more power-efficient data access circuit that avoids the latency and stability issues of a traditional DLL by leveraging a set of stable, internally generated clocks (’946 Patent, col. 2:15-20).

Key Claims at a Glance

  • The complaint asserts independent apparatus claim 1 and dependent claims 2, 3, 7, 8, and 9 (Compl. ¶52).
  • The essential elements of independent claim 1 are:
    • A phase locked loop (PLL) that provides a plurality of internal clocks and selects a strobe clock from them according to a phase selection signal.
    • A data receiving circuit coupled to the PLL, which includes:
      • a latching module to latch a data signal according to triggers from the strobe clock; and
      • a calibrating circuit to generate the phase selection signal by comparing training data with predetermined data in a training mode and determining the signal corresponding to a preferred clock for use in a normal mode.
  • The complaint reserves the right to assert additional claims (Compl. ¶52, n.5).

U.S. Patent No. 8,451,211 - “Dimming control apparatus and method for generating dimming control signal by referring to distribution information/multiple characteristic values derived from pixel values”

  • Technology Synopsis: The patent addresses methods for controlling the backlight of a display to improve image quality (’211 Patent, Background). The patented solution involves a data analysis module that receives pixel values for a video frame, derives a characteristic value based on the distribution of those pixels (e.g., from a histogram), and generates a dimming value based on that characteristic value to control the backlight (’211 Patent, Abstract).
  • Asserted Claims: Claims 5, 14, and 15 are asserted (Compl. ¶70).
  • Accused Features: The complaint accuses Snapdragon processors that support the HDR10+ codec, alleging this functionality performs the claimed dimming control methods (Compl. ¶68, ¶73).

U.S. Patent No. 8,462,846 - “Video encoder and method for performing intra-prediction and video data compression”

  • Technology Synopsis: The patent relates to intra-prediction in video compression, which can suffer from "discontinuous change in predicted block values" between adjacent blocks (’846 Patent, col. 2:12-14). The proposed solution is a method that determines prediction modes for a current block as well as its neighboring left and up blocks, calculates separate prediction values for a target pixel based on these modes, and then weight-averages the results to obtain a smoother, more accurate final prediction value (’846 Patent, Abstract).
  • Asserted Claims: Claims 1, 2, 3, 5, and 8 are asserted (Compl. ¶88).
  • Accused Features: The complaint accuses Snapdragon processors that support the AV1 video decoding standard, which allegedly uses the claimed intra-prediction methods (Compl. ¶86, ¶90-91).

U.S. Patent No. 9,066,013 - “Content-adaptive image resizing method and related apparatus thereof”

  • Technology Synopsis: The patent addresses content-adaptive image resizing, particularly for deblurring images captured by devices like smartphones where hand shake is common (’013 Patent, Background). The invention is a method that performs an image content analysis on an input image and then creates a target image by scaling the input image according to the analysis result, which allows for different resizing settings to be applied to different image regions based on their content (e.g., blur level) (’013 Patent, Abstract).
  • Asserted Claims: Claims 7 and 18 are asserted (Compl. ¶108).
  • Accused Features: The complaint accuses Snapdragon processors that support the AV1 video encoding standard, alleging that features like in-loop frame super-resolution perform the claimed resizing method (Compl. ¶106, ¶110-111).

U.S. Patent No. 9,813,730 - “Method and apparatus for fine-grained motion boundary processing”

  • Technology Synopsis: The patent addresses motion boundary processing in video coding to reduce visual artifacts at the edges of coding units (CUs) (’730 Patent, Background). The solution involves deriving "pre-generated predictors" based on the motion vectors of neighboring CUs and storing them. A final predictor for a boundary pixel of the current CU is then generated by combining its own motion-compensated predictor with the stored pre-generated predictors from its neighbors, creating a smoother transition (’730 Patent, Abstract).
  • Asserted Claims: Claims 9, 10, 11, 16, and 18 are asserted (Compl. ¶126).
  • Accused Features: The complaint accuses Snapdragon processors that support the AV1 video decoding standard, alleging that its overlapped block motion compensation (OBMC) functionality infringes the patent (Compl. ¶124, ¶129, ¶131).

III. The Accused Instrumentality

Product Identification

The complaint identifies the "Accused Instrumentalities" as Qualcomm processors, including the Snapdragon 4, 6, 7, 8, and X Series product lines, and other processors and platforms sold by Defendant (Compl. ¶10).

Functionality and Market Context

The accused products are systems-on-a-chip (SoCs) that function as the central processing units for a wide variety of electronic devices (Compl. ¶5). The infringement allegations focus on specific technical functionalities within these SoCs. For the ’089 and ’946 Patents, the functionality is the LPDDR5/5X memory controller used for high-speed memory access (Compl. ¶33, ¶50). For the ’211 Patent, the accused functionality is dimming control for displays supporting the HDR10+ standard (Compl. ¶68). For the ’846, ’013, and ’730 Patents, the accused functionality is the hardware and software implementation of the AV1 video coding standard (Compl. ¶86, ¶106, ¶124). The complaint alleges Defendant is one of the world's largest manufacturers of integrated circuits for the wireless device industry, suggesting the accused products have substantial market penetration (Compl. ¶5). The complaint provides a screenshot from a product brief for the Snapdragon 8 Gen 2 processor, highlighting its memory specifications (Compl. ¶37).

IV. Analysis of Infringement Allegations

’089 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
detecting a delay calibrating parameter during a first period The accused products' memory controller performs "Read DQ Calibration Training," which allegedly detects a delay calibrating parameter by issuing Read DQ Calibration (RDC) commands to read calibration patterns. ¶38, ¶39 col. 6:21-30
delaying the strobe signal by a predetermined phase according to the delay calibrating parameter during a second period During a subsequent "burst read operation" (the second period), the memory controller uses the result of the prior calibration to delay the RDQS (strobe signal) for data access. ¶40 col. 6:50-59

Identified Points of Contention

  • Scope Questions: A central question may be whether the operations defined by the JEDEC LPDDR5 standard for "Read DQ Calibration" fall within the scope of the claim term "detecting a delay calibrating parameter." Defendant could argue that its standard-compliant implementation is technically distinct from the specific two-period calibration method described and claimed in the patent.
  • Technical Questions: The analysis will likely focus on what specific "parameter" is detected and how it is used. The complaint alleges the controller detects a delay parameter (Compl. ¶39), and the patent describes determining a number of buffers 'N' (’089 Patent, Abstract). The court may need to determine if the process of issuing RDC commands and adjusting for "SoC receive delays" and "Vref" (Compl. ¶38) is functionally the same as the patented method of detecting a transition point in a delay chain to determine a buffer count.

’946 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a data access apparatus, for accessing a memory that provides a data signal to the data access apparatus The accused Snapdragon processor (Controller) is a data access apparatus that accesses LPDDR5 SDRAM (memory), which provides a data signal (DQ). A block diagram shows the Controller and SDRAM (Compl. ¶55). ¶55 col. 4:21-26
a phase locked loop (PLL) that provides a plurality of internal clocks and selects a strobe clock from the plurality of internal clocks according to a phase selection signal The controller contains a PLL that provides internal clocks (WCK). The complaint alleges the controller selects a strobe clock by adjusting the "WCK_t and WCK_c delay setting" based on feedback during a training procedure. A block diagram shows the PLL and Phase Controller (Compl. ¶56). ¶56, ¶59 col. 3:51-57
a data receiving circuit coupled to the PLL The accused apparatus includes a data receiving circuit, shown coupled to the PLL in an annotated block diagram (Compl. ¶57). ¶57 col. 4:27-28
a latching module that latches the data signal according to a plurality of triggers of the strobe clock The data receiving circuit contains a latching module that latches the data signal (DQ) based on the triggers of the selected strobe clock (RDQS). An annotated block diagram illustrates this function (Compl. ¶58). ¶58 col. 4:32-34
a calibrating circuit that generates the phase selection signal for comparing a training data with a predetermined data...in a training mode, and determines whether the phase selection signal corresponds to a preferred clock in a normal mode The controller performs a "WCK2CK Leveling Procedure" (training mode) where it receives feedback from the SDRAM to increment or decrement the WCK delay setting (phase selection signal) until the proper delay is established for use in normal operation. ¶59 col. 4:35-43

Identified Points of Contention

  • Scope Questions: The dispute may turn on the definition of "preferred clock." Plaintiff's theory appears to be that any internal clock selected after a training procedure for use in normal operation meets this definition. Defendant may argue the term is limited by the specification to a clock selected based on a "middle phase" criterion among multiple candidate clocks, a detail not explicitly alleged for the accused products (’946 Patent, col. 5:30-40).
  • Technical Questions: A key question will be whether the feedback mechanism in the JEDEC "WCK2CK Leveling Procedure," which the complaint alleges involves incrementing or decrementing a delay setting (Compl. ¶59), is functionally equivalent to the claimed "calibrating circuit" that "compares a training data with a predetermined data" to generate a "phase selection signal."

V. Key Claim Terms for Construction

’089 Patent: "delay calibrating parameter"

  • The Term: "delay calibrating parameter" (Claim 1)
  • Context and Importance: This term is the output of the first step of the claimed method and the input to the second. The entire infringement theory rests on the accused products "detecting" such a parameter during their calibration phase. Practitioners may focus on this term because its scope will determine whether a standard-compliant memory controller calibration process reads on the claim.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language itself is broad and does not specify the form of the parameter. The Abstract describes the invention as "determining N buffers," suggesting the parameter could be any value representing this number (’089 Patent, Abstract).
    • Evidence for a Narrower Interpretation: The detailed description and figures illustrate a specific method for deriving the parameter by sampling the outputs of a delay chain, detecting a transition from '1' to '0', and storing the transition position as a "calibration value" (’089 Patent, col. 6:21-50; Fig. 4). This could support an argument that the term is limited to a parameter determined in this specific manner.

’946 Patent: "preferred clock"

  • The Term: "preferred clock" (Claim 1)
  • Context and Importance: This is the ultimate output of the "calibrating circuit" in "training mode" and is used for data sampling in "normal mode." Whether the accused device determines a "preferred clock" as claimed is central to the infringement analysis.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The Abstract states the calibrating circuit determines a "phase selection signal corresponding to a preferred clock used in a normal mode," which could broadly cover any clock chosen through a calibration process for subsequent use (’946 Patent, Abstract).
    • Evidence for a Narrower Interpretation: The detailed description specifies a more particular selection process, stating that if "there are a plurality of candidate clocks, the calibrating circuit 32 selects a preferred clock having a middle phase from the candidate clocks" (’946 Patent, col. 5:30-34). This language may support a narrower construction requiring a "middle phase" selection criterion.

VI. Other Allegations

  • Indirect Infringement: For each of the six asserted patents, the complaint alleges inducement of infringement under 35 U.S.C. § 271(b). The allegations are based on Defendant knowingly and intentionally encouraging infringement by its customers and partners through actions such as "creating and disseminating advertisements and instructive materials," providing "technical documentation and tools," and incorporating "instructions in the form executable code or logic that causes performance of claimed methods" (e.g., Compl. ¶¶ 42-43, 60-61, 78-79).
  • Willful Infringement: The complaint alleges willful infringement for all asserted patents. The basis for willfulness is alleged pre-suit knowledge stemming from correspondence sent to Defendant on November 30, 2023, and February 20, 2025, which allegedly identified the patents and included "exemplary charts detailing Qualcomm's infringement" (Compl. ¶25, ¶26). The complaint further alleges that Defendant "disregarded an objectively high likelihood of infringement" by continuing its conduct after receiving this notice (e.g., Compl. ¶44, ¶62, ¶80).

VII. Analyst’s Conclusion: Key Questions for the Case

  • Standard Implementation vs. Patented Method: A central question, particularly for the memory interface patents ('089, '946), will be whether implementing a public industry standard (JEDEC LPDDR5) is functionally equivalent to practicing the specific methods claimed in the patents. The case may turn on whether the court views the standard's procedures as a distinct, non-infringing technical alternative or as a direct embodiment of the patented inventions.
  • Evidentiary Proof of Infringement: For the video coding patents ('846, '013, '730), the complaint ties infringement to the accused products' support for the AV1 standard, citing technical papers that describe how the standard works. A key evidentiary question will be whether Plaintiff can demonstrate through source code analysis, testing, or internal documents that Defendant's specific commercial implementation of the AV1 codec practices each limitation of the asserted claims, moving the allegations from the level of the standard to the operation of the accused silicon.
  • Scope of Functional Claim Language: The construction of functional claim terms such as "delay calibrating parameter" ('089 Patent) and "preferred clock" ('946 Patent) will be critical. The dispute will likely focus on whether these terms should be interpreted broadly to cover any mechanism that achieves a similar result, as suggested by the complaint's allegations, or whether they are implicitly limited to the specific circuit structures and algorithms detailed in the patent specifications.