Kmizra LLC v. NXP Semiconductors NV

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: K.Mizra LLC (Delaware)
  • Defendant: NXP Semiconductors N.V. (Netherlands), NXP BV. (Netherlands), and NXP USA, Inc. (Delaware)
  • Plaintiff’s Counsel: Nelson Bumgardner Conroy PC
• Case Identification: 7:25-cv-00304, W.D. Tex., 07/08/2025
• Venue Allegations: Venue is alleged to be proper in the Western District of Texas because Defendant NXP USA, Inc. maintains regular and established places of business in the district, including its U.S. Corporate Headquarters in Austin. For the foreign defendants, venue is asserted under 28 U.S.C. § 1391(c) as they are foreign entities.
• Core Dispute: Plaintiff alleges that Defendant’s processors and related semiconductor products infringe six patents related to high-speed digital signaling, memory controller operations, and communication channel calibration.
• Technical Context: The technologies at issue concern methods for ensuring signal integrity and operational stability in high-speed data interfaces, such as PCIe and DDR memory, which are fundamental to the performance of modern electronics in automotive, industrial, mobile, and IoT applications.
• Key Procedural History: The complaint alleges that Plaintiff's predecessor-in-interest, Rambus, provided Defendant with notice and claim charts for at least the '887, '556, and '279 patents in May and August 2018. The complaint further alleges that Plaintiff provided additional notice and claim charts for the '887, '556, '279, and '379 patents in June 2024. These allegations of pre-suit knowledge form the basis for the claim of willful infringement.

Case Timeline

Date	Event
2003-04-09	'887 Patent Priority Date
2004-01-28	'556 and '344 Patents Priority Date
2004-08-20	'743 Patent Priority Date
2004-11-29	'279 and '379 Patents Priority Date
2012-05-22	'887 Patent Issue Date
2014-04-08	'556 Patent Issue Date
2016-09-06	'279 Patent Issue Date
2018-05-22	Plaintiff's predecessor allegedly presents patents to Defendant
2018-08-31	Plaintiff's predecessor allegedly presents patents to Defendant
2019-06-25	'379 Patent Issue Date
2019-12-31	'344 Patent Issue Date
2023-01-10	'743 Patent Issue Date
2024-06-07	Plaintiff allegedly sends notice letters to Defendant
2025-07-08	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,183,887 - “High speed signaling system with adaptive transmit pre-emphasis”

• Patent Identification: 8,183,887, "High speed signaling system with adaptive transmit pre-emphasis," issued May 22, 2012.

The Invention Explained

• Problem Addressed: In high-speed signaling systems, electrical pulses disperse and attenuate as they travel, causing inter-symbol interference (ISI) that degrades signal quality (’887 Patent, col. 1:29-43). The patent notes that prior-art attempts to use pre-emphasis to counteract ISI are challenged by transmitter power constraints and data-dependent attenuation, which complicates the generation of an accurate error signal for adaptation (’887 Patent, col. 1:44-2:4).
• The Patented Solution: The invention describes a signaling system with an adaptive transmitter. The system uses feedback from the receiver to adjust the transmitter's pre-emphasis settings, which are controlled by tap weights associated with multiple output drivers (’887 Patent, col. 2:5-15; Abstract). The receiver generates an indication of whether the received signal exceeds an adaptively determined threshold, and this feedback allows the transmitter's update circuit to adjust the tap weights to optimize signal integrity (’887 Patent, Abstract).
• Technical Importance: This adaptive pre-emphasis technique allows high-speed links to dynamically compensate for channel impairments, which is critical for maintaining reliable communication as data rates increase into the multi-gigabit-per-second range (’887 Patent, col. 1:24-28).

Key Claims at a Glance

• The complaint asserts independent claim 19 (Compl. ¶68).
• Claim 19 is directed to an apparatus comprising:
  • A set of drivers to transmit a digital sequence to a receiver, each driver controlled in association with one of a plurality of taps, each tap having a tap weight to control a drive strength of the driver.
  • An update circuit to update a tap weight associated with at least one of the plurality of taps responsive to feedback from the receiver, the feedback representing a setting for the at least one of the plurality of taps, the feedback adjusted to compensate for a target signal level.
• The complaint reserves the right to assert additional claims (Compl. ¶68, n.1).

U.S. Patent No. 8,693,556 - “Communication channel calibration for drift conditions”

• Patent Identification: 8,693,556, "Communication channel calibration for drift conditions," issued April 8, 2014.

The Invention Explained

• Problem Addressed: In high-speed communication channels, system conditions such as temperature and voltage can drift over time, altering the optimal timing points for data transmission and reception (’556 Patent, col. 2:44-51). While initial calibration can establish an optimal setting, this setting can become suboptimal due to drift. Recalibrating using the initial, exhaustive process can interfere with normal system operation (’556 Patent, col. 2:51-64).
• The Patented Solution: The patent discloses a method for periodically calibrating a communication parameter to track and compensate for drift. The system first establishes an initial "operation value" for a parameter (e.g., timing) through a calibration sequence. Then, during normal operation, it determines "adjustment information" for that parameter, interspersed with data transmission, and uses this information to adjust the operation value (’556 Patent, col. 3:33-40; Abstract). This allows for ongoing drift compensation without halting data flow for a full recalibration (’556 Patent, col. 3:5-12).
• Technical Importance: This approach enables communication systems to maintain optimal performance and reliability over time and across varying environmental conditions by making minor adjustments during operation, rather than requiring disruptive, full-scale recalibrations (’556 Patent, col. 2:65-3:4).

Key Claims at a Glance

• The complaint asserts independent claim 10 (Compl. ¶90).
• Claim 10 is directed to an integrated circuit comprising:
  • An interface for a communication channel.
  • Logic to apply a parameter associated with transmission of data on the communication channel.
  • Logic to process a calibration sequence to establish an operation value that represents the parameter, and to transmit or receive data in accordance with the operation value.
  • Logic to determine adjustment information for the parameter, interspersed with said transmission or reception of data on the communication channel.
  • Logic to adjust the operation value for the parameter using said adjustment information.
• The complaint reserves the right to assert additional claims (Compl. ¶68, n.1).

U.S. Patent No. 9,437,279 - “Memory controller with clock-to-strobe skew compensation”

• Patent Identification: 9,437,279, "Memory controller with clock-to-strobe skew compensation," issued September 6, 2016.

Technology Synopsis

This patent relates to compensating for timing differences (skew) between a clock signal and a data strobe signal in a memory system. The invention involves a timing calibration operation, such as write leveling, where a memory controller outputs a sequence of differently delayed data timing signals to a memory IC to identify a delay value that best compensates for signal propagation time differences, which is then used as a write timing delay (Compl. ¶¶112-113).

Asserted Claims

At least independent claim 11 is asserted (Compl. ¶109).

Accused Features

The accused features are the memory controllers in NXP's processors, such as the i.MX53 Multimedia Processor, that support DDR3 memory and implement write leveling functionality (Compl. ¶¶107, 110, 112).

U.S. Patent No. 10,331,379 - “Memory controller for micro-threaded memory operations”

• Patent Identification: 10,331,379, "Memory controller for micro-threaded memory operations," issued June 25, 2019.

Technology Synopsis

This patent addresses memory controller efficiency by scheduling memory access commands based on the memory device's architecture of bank groups. The invention uses different, specified timing intervals for back-to-back row activations or column accesses depending on whether the banks are within the same bank group or different bank groups, with the interval for same-group accesses being longer than for different-group accesses to improve performance (Compl. ¶¶130, 134-135; '379 Patent, Abstract).

Asserted Claims

At least independent claim 1 is asserted (Compl. ¶129).

Accused Features

The accused features are the DDR4 memory controllers in NXP processors, such as the i.MX 8M Mini, which manage memory devices having a plurality of bank groups and allegedly implement the claimed command scheduling with different timing intervals (Compl. ¶¶127, 130, 133).

U.S. Patent No. 10,523,344 - “Periodic calibration for communication channels by drift tracking”

• Patent Identification: 10,523,344, "Periodic calibration for communication channels by drift tracking," issued December 31, 2019.

Technology Synopsis

This patent describes a method for calibrating a component to account for operational drift. The method involves a first, exhaustive calibration during an initialization sequence to establish an initial parameter value (e.g., driver strength or termination resistance). Subsequently, during normal operation, a second, periodic calibration is performed to update the parameter value, particularly in response to a switch between operational modes (e.g., exiting a power-down state) (Compl. ¶¶148-150).

Asserted Claims

At least independent claim 1 is asserted (Compl. ¶147).

Accused Features

The accused features are memory controllers in NXP processors, such as the i.MX 7Dual, that perform ZQ calibration to calibrate external SDRAM for parameters like driver impedance (RON) and on-die termination (ODT) to account for process, voltage, and temperature (PVT) variations (Compl. ¶¶145, 148-149).

U.S. Patent No. 11,551,743 - “Strobe-offset control circuit”

• Patent Identification: 11,551,743, "Strobe-offset control circuit," issued January 10, 2023.

Technology Synopsis

This patent relates to a method of operation in a memory controller for calibrating the timing relationship between a data signal (DQ) and a strobe signal (DQS). The controller dispatches a calibration read command, receives calibration read data and the accompanying strobe signal from a memory device, generates a control signal based on a comparison of a data pattern in the received data, and adjusts the phase alignment between the strobe and the data in response (Compl. ¶¶164-167).

Asserted Claims

At least independent claim 6 is asserted (Compl. ¶163).

Accused Features

The accused features are the LPDDR4 memory controllers in NXP processors, such as the i.MX 8M Mini, that perform "Write DQS2DQ Training," a process alleged to meet the claim limitations (Compl. ¶¶161, 164).

III. The Accused Instrumentality

Product Identification

The complaint accuses a range of NXP's semiconductor products, primarily its application processors and processing platforms. Specific examples cited include the Layerscape family (e.g., LX2162A), the i.MX Applications Processors family (e.g., i.MX 7Dual, i.MX 8M Mini, i.MX53), and the S32 Automotive Processing Platform (Compl. ¶¶66, 88, 107, 127, 145, 161).

Functionality and Market Context

The accused products are highly integrated systems-on-chip (SoCs) that serve as the core processing units in a wide array of devices, including automotive, industrial, IoT, and mobile applications (Compl. ¶14). The specific functionalities accused of infringement are the high-speed communication interfaces embedded within these processors, namely their PCIe (Peripheral Component Interconnect Express) controllers and their DDR (Double Data Rate) memory controllers for various standards like LPDDR3, LPDDR4, and DDR3 (Compl. ¶¶66, 88, 107). These interfaces are critical for high-bandwidth communication between the processor and other system components like memory and peripherals, directly impacting overall system performance. A screenshot from an NXP datasheet illustrates that the accused LX2162A processor contains "Three PCI express 3.0 controllers" (Compl. ¶69). Another visual from an NXP reference manual identifies a "DDR Memory Controller (DDRMC)" in the accused i.MX 7Dual processor (Compl. ¶92).

IV. Analysis of Infringement Allegations

'887 Patent Infringement Allegations

Claim Element (from Independent Claim 19)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
an apparatus comprising: a set of drivers to transmit a digital sequence to a receiver, each driver controlled in association with one of a plurality of taps...	The accused processors, such as the LX2162A, support PCIe 3.0, which defines feed-forward equalization (FFE) using transmitters configured with multiple "taps" or "boost drivers."	¶71	col. 4:1-6
...each tap having a tap weight to control a drive strength of the driver; and	The FFE in the accused products is configured with taps having coefficients that control their drive strength to emphasize or de-emphasize frequency aspects of the transmitted signal. A diagram from the PCIe specification illustrates these taps and their coefficients (c-1, c0, c+1) controlling drive strength.	¶¶71, 75	col. 4:7-14
an update circuit to update a tap weight associated with at least one of the plurality of taps responsive to feedback from the receiver...	The accused products' PCIe interface performs "link training" or "backchannel training," where the receiver evaluates the signal and communicates back to the transmitter how to adjust its FFE settings (tap weights/coefficients).	¶¶70, 76, 77	col. 4:15-22
...the feedback representing a setting for the at least one of the plurality of taps, the feedback adjusted to compensate for a target signal level.	During link training, the receiver requests different coefficient settings from the transmitter to evaluate which setting achieves the best signal quality. The process continues until the receiver is satisfied, thereby adjusting the coefficients to compensate for frequency-dependent losses and achieve a target signal level.	¶¶77, 78	col. 4:23-26

Identified Points of Contention

• Scope Questions: A primary question may be whether the "link training" procedure defined by the PCIe standard, where an upstream port (receiver) requests specific coefficient changes from a downstream port (transmitter), constitutes "feedback from the receiver" as contemplated by the patent. The dispute could center on whether these standardized protocol messages are equivalent to the adaptive feedback mechanism described in the patent specification.
• Technical Questions: The analysis may focus on whether the "update circuit" is part of the NXP processor itself or a function of the overall system implementing the PCIe protocol. The complaint alleges the processor's FFE circuit performs the update, but a defendant may argue the update logic is dictated by the standard and not a distinct inventive circuit within the accused product.

'556 Patent Infringement Allegations

Claim Element (from Independent Claim 10)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
an integrated circuit comprising: an interface for a communication channel;	The accused products, such as the i.MX 7Dual processor, are integrated circuits that include a DDR Memory Controller (DDRMC) providing an interface to an LPDDR3 memory channel.	¶¶91, 92	col. 4:18-20
logic to apply a parameter associated with transmission of data on the communication channel;	The DDRMC includes logic to apply the tDQSS parameter, which governs the clock-to-data-strobe signal relationship, ensuring proper timing for data transmission.	¶¶93, 94	col. 4:21-23
logic to process a calibration sequence to establish an operation value that represents the parameter, and to transmit or receive data in accordance with the operation value;	The DDRMC performs a "Write Leveling" calibration sequence. This process establishes an optimal operation value for the tDQSS parameter by adjusting DQS delay settings. Data is then transmitted using this calibrated value.	¶94	col. 4:24-29
logic to determine adjustment information for the parameter, interspersed with said transmission or reception of data on the communication channel; and	The complaint alleges that LPDDR3 devices are subject to temperature and voltage drift. It alleges that write leveling is performed "from time to time, interspersed with data transmission" to determine the adjustment needed for the tDQSS parameter to account for this drift.	¶95	col. 4:30-34
logic to adjust the operation value for the parameter using said adjustment information.	The DDRMC logic adjusts the DQS delay based on the adjustment information determined during the periodic write leveling, thereby adjusting the tDQSS operation value to account for drift.	¶96	col. 4:35-37

Identified Points of Contention

• Scope Questions: The term "interspersed with said transmission or reception of data" may be a central point of dispute. The key question will be whether performing a calibration like write leveling periodically "from time to time" meets this limitation, or if the claim requires the determination of adjustment information to occur concurrently or interwoven with individual data bursts, rather than in separate calibration intervals between periods of data transmission.
• Technical Questions: A factual question may arise regarding how and when the accused products actually perform recalibration for drift. The complaint alleges this occurs to account for temperature and voltage drift, but the evidence for the frequency and specific trigger for this recalibration during normal operation (as opposed to initialization) will be critical.

V. Key Claim Terms for Construction

'887 Patent - "feedback from the receiver"

• The Term: "feedback from the receiver"
• Context and Importance: This term is the core of the adaptive mechanism in claim 19. The infringement theory depends on the standardized "link training" messages in the PCIe protocol qualifying as this "feedback." The construction of this term will determine whether a standard-compliant implementation infringes.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the feedback functionally as information that allows the transmitter to "adjust the threshold level" or "adjust a drive strength" to compensate for signal degradation (’887 Patent, Abstract). This functional description could be argued to read on the PCIe training sequences, which serve the same ultimate purpose.
  • Evidence for a Narrower Interpretation: The detailed description focuses on an "error sign value" (sgn(eₙ)) generated by an "adaptive sampler" at the receiver based on a comparison to a "data level threshold" (’887 Patent, col. 9:10-24). This suggests a specific type of feedback generation that may be narrower than the message-based coefficient requests in the PCIe standard.

'556 Patent - "interspersed with said transmission or reception of data"

• The Term: "interspersed with said transmission or reception of data"
• Context and Importance: This limitation defines when the "adjustment information" is determined. The infringement allegation hinges on periodic calibration events qualifying as "interspersed." If this term is construed to require the adjustment to happen concurrently with or between individual bits/bytes of a data packet, the infringement case may be more difficult than if it is construed to mean happening in intervals between larger data transmission sessions.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent's goal is to track drift "during normal operation" without the disruption of a full, exhaustive calibration (’556 Patent, col. 2:44-54). This purpose could support an interpretation where "interspersed" means any calibration activity that occurs between periods of normal data flow, without requiring a full system halt.
  • Evidence for a Narrower Interpretation: The claim language recites determining adjustment information "interspersed with said transmission or reception of data," which could be argued to tie the act of determining adjustment information directly to the same data stream being transmitted or received, rather than as a separate, intervening process.

VI. Other Allegations

Indirect Infringement

The complaint alleges inducement of infringement across all asserted patents. The basis for this allegation is that Defendant provides technical documentation, data sheets, fact sheets, reference manuals, and application notes that instruct customers and end-users on how to configure and use the accused functionalities (e.g., the PCIe and DDR interfaces) in an infringing manner (Compl. ¶¶ 80-81, 99-100, 119, 137, 153, 169).

Willful Infringement

The complaint alleges willful infringement based on Defendant's alleged pre-suit knowledge of the patents. It asserts that Plaintiff's predecessor, Rambus, presented claim charts demonstrating infringement by NXP products for at least the '887, '556, and '279 patents as early as May 2018. It further alleges Plaintiff sent its own notice letters with claim charts in June 2024, more than a year before the complaint was filed (Compl. ¶59).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be one of Standard-Compliant Infringement: Can routine, standardized industry protocols for ensuring signal integrity—specifically PCIe link training and DDR memory write leveling—be construed to practice the specific methods and structures claimed in the patents-in-suit? The case will likely require a detailed comparison of the steps mandated by the standards with the specific limitations recited in the asserted claims.
• A key evidentiary question will be one of Operational Reality vs. Allegation: For patents focused on periodic drift calibration ('556 and '344 patents), the case may depend on factual evidence of how and when the accused NXP processors perform recalibration during normal, prolonged operation. A core question for the court will be whether these processors perform the claimed periodic, interspersed calibration to track environmental drift, or if such calibration is primarily limited to system initialization.
• A third core issue will be one of Definitional Scope: The interpretation of terms like "feedback from the receiver" ('887 Patent) and "interspersed with...data" ('556 Patent) will be critical. The outcome may turn on whether these terms are given a broad, functional meaning that could encompass standard protocol operations, or a narrower meaning limited to the specific circuit implementations and processes detailed in the patent specifications.