Kmizra LLC v. NXP Semiconductors NV

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: K.Mizra LLC (Delaware)
  • Defendant: NXP USA, Inc. (Delaware)
  • Plaintiff’s Counsel: Nelson Bumgardner Conroy PC
• Case Identification: 7:25-cv-00304, W.D. Tex., 11/12/2025
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant maintains regular and established places of business in the District, including its U.S. Corporate Headquarters in Austin.
• Core Dispute: Plaintiff alleges that Defendant’s semiconductor processors, which are used in automotive, IoT, and communication infrastructure applications, infringe six patents related to high-speed signaling, memory controller operations, and communication channel calibration.
• Technical Context: The technologies at issue address fundamental challenges in high-speed digital communication, such as compensating for signal degradation in peripheral component interconnect express (PCIe) interfaces and managing timing and drift in various types of dynamic random-access memory (DDR SDRAM).
• Key Procedural History: The complaint alleges that Defendant had pre-suit knowledge of the asserted patents and its infringement. It states that Plaintiff's predecessor-in-interest, Rambus, presented claim charts to NXP in 2018 identifying infringement by NXP products. Plaintiff also alleges it sent letters with exemplary claim charts to NXP in 2024. This history forms the basis for Plaintiff's claims of willful infringement.

Case Timeline

Date	Event
2004-01-28	’466 Patent Priority Date
2004-08-20	’608 Patent Priority Date
2004-11-29	’379 Patent Priority Date
2010-01-25	’887 Patent Priority Date
2012-05-22	’887 Patent Issue Date
2013-03-18	’556 Patent Priority Date
2014-04-08	’556 Patent Issue Date
2015-08-18	’608 Patent Issue Date
2015-10-13	’466 Patent Issue Date
2015-11-24	’279 Patent Priority Date
2016-09-06	’279 Patent Issue Date
2018-05-22	Rambus presentation to NXP alleged
2019-06-25	’379 Patent Issue Date
2024-06-07	K.Mizra letter to NXP alleged
2025-11-12	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,183,887 - "High speed signaling system with adaptive transmit pre-emphasis," issued May 22, 2012

The Invention Explained

• Problem Addressed: The patent addresses signal degradation in high-speed signaling systems caused by inter-symbol interference (ISI), where electrical pulses disperse and interfere with one another (’887 Patent, col. 1:16-41). It also notes the difficulty of creating an adaptive system when transmitter power constraints prevent signals from reaching their ideal, non-attenuated levels, making it difficult to generate a useful error signal for feedback (’887 Patent, col. 2:9-24).
• The Patented Solution: The invention is an adaptive system where the receiver uses an "adaptive data level threshold" (DLEV) to evaluate the incoming signal. This generates not only the data bit but also an "error sign" that indicates whether the signal was above or below the DLEV (’887 Patent, Abstract; Fig. 3). This error sign, along with a history of past data, is used to update the transmitter's pre-emphasis "tap weights" (’887 Patent, col. 4:52-60). Crucially, the DLEV itself is updated based on the error, allowing the receiver to "learn" the attenuated signal level of the channel and guide the transmitter to an optimal setting even under power constraints (’887 Patent, col. 11:45-51).
• Technical Importance: This adaptive method enables high-speed data links to automatically compensate for channel-specific distortions without prior knowledge of the channel, enhancing performance and reliability in standardized interfaces like PCIe (’887 Patent, col. 1:16-24).

Key Claims at a Glance

• The complaint asserts independent apparatus claim 19 (’887 Patent, col. 54:53-67; Compl. ¶57).
• Essential elements of claim 19 include:
  • A set of drivers for transmitting a digital sequence, each controlled by one of a plurality of taps.
  • Each driver having a drive strength controlled by a tap weight.
  • An update circuit to update a tap weight responsive to feedback from a receiver.
  • The feedback represents a setting for a tap and is "adjusted to compensate for a target signal level."
• The complaint reserves the right to assert additional claims (Compl. ¶57, n.1).

U.S. Patent No. 8,693,556 - "Communication channel calibration for drift conditions," issued April 8, 2014

The Invention Explained

• Problem Addressed: The patent family addresses the problem of "drift" in communication channels, where parameters like timing and voltage change from their initial settings due to environmental factors like temperature (’556 Patent family member, U.S. Patent No. 10,523,344, col. 2:42-50). Repeatedly running the comprehensive calibration sequence used at system initialization is disruptive and degrades performance (’556 Patent family member, U.S. Patent No. 10,523,344, col. 2:50-62).
• The Patented Solution: The invention proposes a two-tiered calibration method. First, an "exhaustive" calibration using long, complex data patterns establishes an optimal initial value for an operating parameter (’556 Patent, Abstract). Subsequently, during normal operation, a simpler and less disruptive "second calibration sequence" using short patterns is executed periodically to measure only the drift from that initial value. This measured drift is then used to update the original operation value, keeping the channel optimized without the overhead of a full recalibration (’556 Patent family member, U.S. Patent No. 10,523,344, col. 3:15-24; Fig. 8).
• Technical Importance: This approach allows high-speed interfaces, such as those for DDR memory, to maintain optimal performance across changing operating conditions without the significant performance penalty associated with repeatedly executing a full, resource-intensive calibration procedure (’556 Patent family member, U.S. Patent No. 10,523,344, col. 1:21-31).

Key Claims at a Glance

• The complaint asserts independent integrated circuit claim 10 (’556 Patent, col. 22:10-29; Compl. ¶78).
• Essential elements of claim 10 include:
  • An interface for a communication channel.
  • Logic to apply a parameter associated with data transmission.
  • Logic to process a calibration sequence to establish an operation value for the parameter.
  • Logic to determine adjustment information for the parameter, with this determination being "interspersed with said transmission or reception of data."
  • Logic to adjust the operation value using the adjustment information.
• The complaint reserves the right to assert additional claims (Compl. ¶57, n.1).

Multi-Patent Capsule: U.S. Patent No. 9,437,279, "Memory controller with clock-to-strobe skew compensation," issued September 6, 2016

• Technology Synopsis: This patent relates to memory controllers that perform timing calibration for memory interfaces like DDR3. It describes a "write leveling" process where a memory controller outputs a sequence of differently delayed data strobe (DQS) signals to a memory IC, identifies the DQS signal that best compensates for signal propagation differences between the clock (CK) and DQS lines, and selects that delay as a write timing delay for subsequent write operations (’279 Patent, Abstract).
• Asserted Claims: Independent claim 11 is asserted (Compl. ¶97).
• Accused Features: The complaint alleges that NXP's i.MX53 Multimedia Processor, which includes a memory controller supporting DDR3, infringes by performing a "write leveling" calibration operation to compensate for timing differences between DQS and CLK signals (Compl. ¶¶98-101).

Multi-Patent Capsule: U.S. Patent No. 10,331,379, "Memory controller for micro-threaded memory operations," issued June 25, 2019

• Technology Synopsis: This patent describes a memory controller architecture for "micro-threaded" memory operations, designed to improve efficiency. The controller schedules row activation and column access commands to different bank groups within a memory device (e.g., DDR4 SDRAM) using different timing intervals for accesses within the same bank group versus accesses to different bank groups, such as tRRD_L/S (row-to-row delay) and tCCD_L/S (column-to-column delay) (’379 Patent, Abstract; col. 6:49-67).
• Asserted Claims: Independent claim 1 is asserted (Compl. ¶117).
• Accused Features: NXP's i.MX 8M Mini processor, which contains a DDR4 memory controller, is accused of infringing by scheduling row activation and column access commands according to the different timing intervals (tRRD_L > tRRD_S and tCCD_L > tCCD_S) specified for same versus different bank groups in the DDR4 standard (Compl. ¶¶118, 121-123).

Multi-Patent Capsule: U.S. Patent No. 9,160,466, "Periodic calibration for communication channels by drift tracking," issued October 13, 2015

• Technology Synopsis: This patent relates to the same two-tiered calibration technology as the ’556 Patent. It describes a method where a receive component undergoes a first, extensive calibration (e.g., ZQInit) at initialization to set a parameter value (e.g., on-die termination resistance). Subsequently, it undergoes a periodic, shorter second calibration (e.g., ZQCS) to update that value to account for drift from operating voltage or temperature changes (’466 Patent, Abstract).
• Asserted Claims: Independent claim 1 is asserted (Compl. ¶135).
• Accused Features: The i.MX 7Dual Processor is accused of infringing by performing an initial ZQ calibration (ZQInit) on an LPDDR3 SDRAM at power-up and then performing periodic short ZQ calibrations (ZQCS) to update the termination and driver impedance values to account for voltage and temperature variations (Compl. ¶¶136-138).

Multi-Patent Capsule: U.S. Patent No. 9,111,608, "Strobe-offset control circuit," issued August 18, 2015

• Technology Synopsis: This patent describes a circuit for per-pin timing calibration in memory systems with unmatched data (DQ) and strobe (DQS) signal paths, such as LPDDR4. The controller receives data and strobe signals and uses adjustable delay elements for each individual data signal line. During a training mode (e.g., DQS2DQ training), the delay for each DQ signal is adjusted relative to the DQS signal to center the data eye at the receiver latch, with the resulting delay value used for subsequent operations (’608 Patent, Abstract).
• Asserted Claims: Independent claim 1 is asserted (Compl. ¶151).
• Accused Features: The DDR controller in NXP's i.MX 8M Mini Applications Processor is accused of infringing by performing "Write DQS2DQ Training" for its LPDDR4 interface. This process allegedly involves delaying the individual DQ data signals relative to the DQS strobe signal to center-align the data eye at the receiver latch (Compl. ¶¶152, 153).

III. The Accused Instrumentality

Product Identification

The complaint names several categories of NXP processors, including Layerscape Processors, i.MX Applications Processors, and S32 Automotive Processing Platforms (Compl. ¶¶55, 76, 95, 115, 133, 149). Specific exemplars identified are the LX2162A Processor, the i.MX 7Dual Applications Processor, the i.MX53 Multimedia Processor, and the i.MX 8M Mini Applications Processor (Compl. ¶¶55, 76, 98, 118).

Functionality and Market Context

The accused products are semiconductor processors that serve as the core of a wide range of electronic systems, including automotive, industrial & IoT, mobile, and communication infrastructure (Compl. ¶11). The complaint focuses on the technical functionality of their high-speed interfaces for communicating with other system components. These interfaces allegedly include PCIe 3.0 for peripheral communication and memory controllers for various generations of DDR memory, including DDR3, LPDDR3, and LPDDR4, which are industry-standard technologies for data transfer (Compl. ¶¶55, 76, 95, 115). The complaint alleges these products are commercially significant and that Defendant derives substantial revenue from their sale (Compl. ¶29).

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,183,887 Infringement Allegations

Claim Element (from Independent Claim 19)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
an apparatus, comprising: a set of drivers to transmit a digital sequence to a receiver, each driver controlled in association with one of a plurality of taps.	The accused LX2162A processor supports PCIe 3.0, which uses a "coefficient-based equalization mode" with multiple "taps" or "boost drivers" to transmit digital sequences during link training. The complaint references a PCIe specification diagram showing a 3-tap FIR filter representation for transmitter equalization.	¶61	col. 5:36-41
each driver to have a drive strength controlled in association with a tap weight.	The PCIe 3.0 equalization mode allegedly uses "coefficients" (tap weights) to control the "drive strength" of the transmitter's boost drivers (taps) to shape the transmitted signal.	¶63	col. 6:1-6
an update circuit to update a tap weight associated with at least one of the plurality of taps responsive to feedback from the receiver, the feedback representing a setting for the at least one of the plurality of taps, the feedback adjusted to compensate for a target signal level.	During PCIe 3.0 link training, the receiver evaluates the transmitted signal and sends "messaging (feedback)" to the transmitter with requests to update the tap weights (coefficients) until signal quality is optimized for a desired level. The complaint includes a diagram illustrating this "Backchannel process."	¶¶64-66	col. 4:52-60

Identified Points of Contention:

• Scope Questions: The infringement theory maps the functions of the standard PCIe 3.0 link training protocol to the claim language. A potential dispute may arise over whether the "update circuit" required by the claim, which is described in the patent as a specific adaptive mechanism involving a learned "data level threshold" (DLEV), reads on the conventional feedback loop of the PCIe standard. The complaint alleges the feedback is "adjusted to compensate for a target signal level" but does not specify that this target level is adaptively determined in the manner taught by the patent.
• Technical Questions: A key factual question may be how the accused products' PCIe equalization procedure technically operates. Specifically, what evidence does the complaint provide that the "messaging (feedback)" in the PCIe protocol performs the specific function of being "adjusted to compensate for a target signal level" as that phrase is understood in the context of the ’887 Patent, versus simply optimizing an eye diagram according to predefined metrics in the PCIe specification?

U.S. Patent No. 8,693,556 Infringement Allegations

Claim Element (from Independent Claim 10)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
an integrated circuit, comprising: an interface for a communication channel.	The accused i.MX 7Dual processor includes a DDR Memory Controller (DDRMC) and a DFI-compatible PHY, which together form a "complete memory interface solution" for communicating with LPDDR3 memory.	¶80	col. 3:26-31
logic to apply a parameter associated with transmission of data on the communication channel.	The DDRMC allegedly contains logic to apply the "clock to data strobe signal relationship" (tDQSS parameter) during write data transmissions to the LPDDR3 memory.	¶81	col. 3:7-14
logic to process a calibration sequence to establish an operation value that represents the parameter, and to transmit or receive data in accordance with the operation value.	The processor's DDRMC allegedly performs a "write leveling feature," which is described as a calibration sequence. This process establishes an operation value for the tDQSS parameter that is then used for subsequent write operations.	¶82	col. 3:47-53
logic to determine adjustment information for the parameter, interspersed with said transmission or reception of data on the communication channel.	Based on "information and belief," the complaint alleges that the "write leveling" procedure is performed "from time to time, interspersed with data transmission," to determine the "amount of adjustment needed" to account for temperature and voltage drift.	¶83	col. 4:1-5
logic to adjust the operation value for the parameter using said adjustment information.	The DDRMC allegedly includes logic that adjusts the DQS delay based on the determined adjustment information, thereby adjusting the operation value of the tDQSS parameter to compensate for drift.	¶84	col. 4:5-7

Identified Points of Contention:

• Evidentiary Questions: The allegation that write leveling is performed "interspersed with... data" to track drift is made "upon information and belief" (Compl. ¶83). The JEDEC standard for LPDDR3 describes write leveling as part of an initialization and training sequence. A central factual question for the court will be whether the accused products perform this calibration periodically during normal operation to track drift, as claimed, or only at system startup, as is common practice.
• Scope Questions: The patent distinguishes between an exhaustive initial calibration and a simpler periodic drift-tracking calibration. The complaint appears to allege that the same "write leveling" procedure is used for both establishing the initial value and for determining subsequent "adjustment information." This raises the question of whether periodically re-running a full calibration sequence meets the claim limitation of determining "adjustment information," or if that term requires a distinct, less-intensive process specifically for tracking drift, as described in the patent's specification.

V. Key Claim Terms for Construction

For the ’887 Patent (Claim 19):

• The Term: "update circuit"
• Context and Importance: This term defines the mechanism that makes the system adaptive. Its construction will be critical to determining if the standard PCIe equalization feedback loop is equivalent to the specific adaptive system claimed in the patent.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim itself defines the circuit functionally, as a circuit "to update a tap weight... responsive to feedback." Plaintiff may argue that any circuit performing this function, regardless of its specific implementation, falls within the claim's scope.
  • Evidence for a Narrower Interpretation: The specification repeatedly describes the "update circuit" as the "adaptive module 215" which operates by comparing an incoming signal to an adaptive "data level threshold (DLEV)" to generate an "error sign" (’887 Patent, col. 4:45-60; Fig. 3). A defendant may argue that the term "update circuit" is implicitly limited to this disclosed embodiment and its equivalents.

For the ’556 Patent (Claim 10):

• The Term: "adjustment information"
• Context and Importance: This term is key to the patent's concept of periodic drift tracking, as distinct from initial calibration. The infringement analysis may turn on whether the output of the accused periodic "write leveling" process is "adjustment information" or simply a new "operation value."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: Plaintiff may argue that any information determined periodically that results in an adjustment to the parameter's operation value qualifies as "adjustment information." The claim language does not specify how this information must be derived.
  • Evidence for a Narrower Interpretation: The patent family specification distinguishes between a "first calibration sequence" that is "exhaustive" to find an "operation value," and a "second calibration sequence" that is simpler and used to determine a "drift value" (’556 Patent family member, U.S. Patent No. 10,523,344, col. 3:7-24). A defendant may argue that "adjustment information" is limited to a "drift value" determined by a process distinct from and simpler than the initial calibration.

VI. Other Allegations

• Indirect Infringement: For each asserted patent, the complaint alleges induced infringement under 35 U.S.C. § 271(b). The allegations state that NXP knowingly and intentionally induces infringement by providing technical documentation, data sheets, reference manuals, application notes, and training materials that instruct customers and end-users on how to use the accused products in an infringing manner (Compl. ¶¶69, 88, 108, 126, 142, 161).
• Willful Infringement: For each asserted patent, the complaint alleges willful infringement. The basis for willfulness is alleged pre-suit knowledge of the patents and infringement, stemming from communications and claim chart presentations from Plaintiff's predecessor-in-interest, Rambus, dating back to at least 2018, as well as more recent correspondence from Plaintiff in 2024 (Compl. ¶¶48, 49, 70, 89, 109, 127, 143, 162). The complaint alleges that despite this knowledge, NXP continued its infringing conduct.

VII. Analyst’s Conclusion: Key Questions for the Case

The resolution of this case may depend on the court's interpretation of how industry-standard high-speed interface protocols map onto the specific inventive concepts claimed in the asserted patents. The central questions are likely to be:

• A core issue will be one of functional equivalence: Do the standard feedback and calibration mechanisms in interfaces like PCIe and LPDDR (e.g., link training, write leveling, ZQ calibration), as implemented in NXP's products, perform the specific, multi-step adaptive and drift-tracking functions required by the asserted claims, or is there a fundamental mismatch in their technical operation and purpose?
• A second issue will be one of evidentiary proof regarding operation: Can Plaintiff provide sufficient technical evidence to demonstrate that NXP's processors perform calibrations periodically during normal operation to track environmental drift, as alleged "on information and belief," or are these functions confined to a one-time initialization sequence, which may fall outside the scope of claims requiring interspersed or periodic adjustment?
• A final question will be one of claim scope and prosecution history: To what extent are claim terms like "update circuit" and "adjustment information" limited to the specific embodiments disclosed in the patent specifications—such as an adaptive threshold-based error circuit or a simple drift-measurement sequence—versus broader functional interpretations that could read on conventional industry standards?