DCT

7:25-cv-00313

Daedalus Prime LLC v. Google LLC

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I. Executive Summary and Procedural Information

  • Case Name: Daedalus Prime LLC v. Google, LLC
  • Parties & Counsel:
  • Case Identification: 7:25-cv-00313, W.D. Tex., 07/15/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Google maintains regular and established places of business in the district, employs individuals involved in relevant work such as CPU design, and has committed acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s Tensor System-on-Chips (SOCs) and Axion microprocessors infringe five U.S. patents, originally invented by Intel, related to microprocessor power management, cache coherency, and dynamic voltage control.
  • Technical Context: The patents address fundamental challenges in modern microprocessor design, focusing on optimizing the trade-off between performance and power consumption in complex, multi-domain chips used in data centers and consumer electronics.
  • Key Procedural History: The complaint notes that U.S. Patent Nos. 8,775,833 and 8,898,494 have previously survived inter partes review (IPR) proceedings before the Patent Trial and Appeal Board (PTAB), suggesting that at least some claims of these patents have already withstood a validity challenge.

Case Timeline

Date Event
2011-09-06 ’833 Patent Priority Date
2011-12-13 ’228 Patent Priority Date
2011-12-15 ’494 and ’197 Patents Priority Date
2013-03-11 ’167 Patent Priority Date
2014-07-08 ’833 Patent Issue Date
2014-11-25 ’494 Patent Issue Date
2015-03-17 ’228 Patent Issue Date
2019-08-06 ’197 Patent Issue Date
2021-10-19 Google Tensor SOC Announced
2022-11-22 ’167 Patent Issue Date
2024-04-09 Google Axion Processor Announced
2025-07-15 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,775,833 - "Dynamically Allocating a Power Budget Over Multiple Domains of a Processor"

Issued July 8, 2014 (Compl. ¶15).

The Invention Explained

  • Problem Addressed: In a multi-domain processor where different functional units (e.g., CPU cores, graphics engines) share a single power budget, there is a need for a mechanism to intelligently partition that budget as the power demands of each unit change with their respective workloads (’833 Patent, col. 2:10-15).
  • The Patented Solution: The invention provides a method and system for dynamically allocating a variable power budget between different processor domains at runtime. A power control unit determines a total power budget for a given time interval and divides it between a first domain (e.g., cores) and a second domain (e.g., graphics) based on stored "power sharing value[s]," which in turn control the operating frequency of those domains (’833 Patent, Abstract; Compl. ¶17-18). Figure 7 of the patent illustrates a multi-domain processor architecture where a Power Sharing Logic within a Power Control Unit manages this allocation (’833 Patent, Fig. 7).
  • Technical Importance: This technology enables more efficient power management in complex processors, allowing for a better balance between computational performance and thermal or battery life constraints (Compl. ¶14).

Key Claims at a Glance

  • The complaint asserts "one or more claims...including at least Claim 14" (Compl. ¶42). Independent claim 13 is quoted in the complaint (Compl. ¶18).
  • Essential elements of independent claim 13 include:
    • A multicore processor with a first domain (plurality of cores), a second domain (graphics engine), and a third domain (system agent circuitry).
    • The third domain operates at a fixed power budget.
    • The third domain contains "power sharing logic" to dynamically allocate a variable power budget between the first and second domains.
    • The allocation is based at least in part on a first power sharing value stored in a first storage and a second power sharing value stored in a second storage.
    • A dynamic random access memory (DRAM) is coupled to the processor.

U.S. Patent No. 8,898,494 - "Power Budgeting Between a Processing Core, A Graphics Core, And a Bus on an Integrated Circuit When a Limit Is Reached"

Issued November 25, 2014 (Compl. ¶20).

The Invention Explained

  • Problem Addressed: The patent addresses how to balance power and performance between different processing elements on an integrated circuit when an overall power or thermal limit is reached (’494 Patent, col. 1:11-19).
  • The Patented Solution: The invention uses separate monitors to determine the workload of a processing core and a communication bus. When a power limit is active, "balancing control" logic dynamically adjusts power allocation between the core and the bus. This decision is based on a comparison between the measured bus workload and a predefined threshold, with the goal of reducing one component's power consumption while ensuring it remains operational above a low limit (’494 Patent, Abstract; cl. 1).
  • Technical Importance: This allows a processor to make intelligent, fine-grained power trade-offs between computation and data communication to maximize performance within a fixed power envelope (Compl. ¶14).

Key Claims at a Glance

  • The complaint asserts "at least Claim 1" (Compl. ¶54).
  • Essential elements of independent claim 1 include:
    • A processor with an integrated circuit containing a first core, cache memory, and a communication bus.
    • A "core workload monitor" to determine the core's workload.
    • A "bus workload monitor" to determine the bus's workload.
    • "Balancing control" logic that receives the bus workload and dynamically tunes power allocation between the core and the bus.
    • The tuning is based on a power limit for the circuit and a "comparison between the bus workload and a bus workload threshold."
    • Power consumption of either the core or the bus is reduced, with the reduction limited to maintain operation "above a low limit."

U.S. Patent No. 10,372,197 - "User Level Control of Power Management Policies"

Issued August 6, 2019 (Compl. ¶25).

  • Technology Synopsis: The patent addresses the difficulty end-users face in tuning the large number of complex power management features available in modern processors (’197 Patent, col. 2:1-6). The invention provides a simplified control mechanism where a processor's power controller receives a single high-level "energy performance bias" (EPB) value and uses it to update settings for a plurality of underlying power management features, allowing for easier control of the power-versus-performance tradeoff (Compl. ¶27; ’197 Patent, Abstract).
  • Asserted Claims: At least Claim 1 (Compl. ¶66).
  • Accused Features: The complaint accuses Google's Tensor SOCs and Axion microprocessors of infringing the ’197 Patent (Compl. ¶66).

U.S. Patent No. 8,984,228 - "Providing Common Caching Agent for Core and Integrated Input/Output (IO) Module"

Issued March 17, 2015 (Compl. ¶30).

  • Technology Synopsis: The patent addresses a scaling problem in multiprocessor systems where integrating an input/output (IO) component with its own dedicated caching agent increases complexity and "snoop traffic" required to maintain cache coherency (’228 Patent, col. 1:19-25). The invention proposes a single, common caching agent that performs coherency operations for both the processor cores and the integrated IO module, thereby reducing system complexity and the amount of snoop traffic needed (Compl. ¶32; ’228 Patent, Abstract).
  • Asserted Claims: At least Claim 1 (Compl. ¶78).
  • Accused Features: The complaint accuses Google's Tensor SOCs and Axion microprocessors of infringing the ’228 Patent (Compl. ¶78).

U.S. Patent No. 11,507,167 - "Controlling Operating Voltage of a Processor"

Issued November 22, 2022 (Compl. ¶35).

  • Technology Synopsis: The patent addresses the latency that occurs when a processor core must wait for a large voltage increase before it can exit a low-power state or enter a high-frequency (e.g., turbo) mode (’167 Patent, col. 2:55-62). The solution is a multi-phase voltage ramp where a power control unit first instructs a voltage regulator to increase to an interim "safe" voltage—sufficient to allow other cores to wake up—and then initiates a second voltage increase to the final target level, reducing the latency for other components to exit low-power states (Compl. ¶37; ’167 Patent, Abstract).
  • Asserted Claims: At least Claim 1 (Compl. ¶90).
  • Accused Features: The complaint accuses Google's Tensor SOCs and Axion microprocessors of infringing the ’167 Patent (Compl. ¶90).

III. The Accused Instrumentality

Product Identification

The complaint identifies Google's Tensor series of System-on-Chips (SOCs), including the G1, G2, G3, and G4 variants, as well as Google's Axion microprocessors (Compl. ¶8). These are collectively termed the "Accused Products" (Compl. ¶42).

Functionality and Market Context

The Tensor SOCs are designed for and sold in Google's Pixel mobile phones and are marketed as a "milestone for machine learning" (Compl. ¶8, p. 3). The complaint includes a screenshot from a Google blog post announcing the Tensor chip (Compl. p. 3). The Axion processors are described as Google's Arm-based CPUs designed for use in its data centers (Compl. ¶8, p. 4). The complaint alleges these products are central to Google's offerings in consumer electronics, AI, and data center services (Compl. ¶14).

IV. Analysis of Infringement Allegations

The complaint alleges infringement of all five patents but refers to claim chart exhibits (Exhibits A-E) that are not attached to the publicly filed complaint (Compl. ¶42, ¶54, ¶66, ¶78, ¶90). Without these exhibits, a detailed element-by-element analysis of the infringement allegations is not possible based on the provided document. The narrative infringement theory is that the Accused Products—complex, multi-domain processors used for machine learning and data center applications—practice the patented inventions related to dynamic power allocation, workload-based power balancing, and cache management. The complaint reproduces Figure 8 of the ’833 Patent, a block diagram of a multiprocessor system, to illustrate one embodiment of that invention (Compl. p. 8).

  • Identified Points of Contention:
    • '833 Patent Scope Question: The infringement analysis may focus on whether the architectural components of the accused Tensor and Axion chips map onto the claimed "first domain" (cores), "second domain" (graphics engine), and "third domain" (system agent). A potential dispute could arise over whether the more heterogeneous structure of modern SOCs, which may include dedicated AI/ML accelerators, falls within the scope of these claim terms.
    • '494 Patent Technical Question: A key factual question will be whether the accused products' power management systems perform the specific two-part logical test required by Claim 1: tuning power based on both an overall "power limit" and a "comparison between the bus workload and a bus workload threshold." The complaint does not provide specific evidence of how the accused power management algorithms operate.

V. Key Claim Terms for Construction

"power sharing logic" (’833 Patent, Claim 13)

  • Context and Importance: This term is central to the '833 patent's infringement theory, as it defines the mechanism that performs the dynamic allocation of the power budget. The case may turn on whether the functionality of Google's power management unit is equivalent to the claimed "logic."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the logic in functional terms as being able to "perform dynamic control and re-allocation of an available power budget" (’833 Patent, col. 8:40-42). This language may support a construction that is not limited to a specific hardware implementation but covers any logic that achieves this function.
    • Evidence for a Narrower Interpretation: Figure 6 of the patent depicts "Power Sharing Logic 359" as a specific component within a "Power Control Unit 355" (’833 Patent, Fig. 6). A defendant may argue that the term should be construed more narrowly in light of this specific embodiment.

"balancing control" (’494 Patent, Claim 1)

  • Context and Importance: The definition of this term is critical because infringement of Claim 1 requires this "control" to perform a specific set of actions based on specific inputs (a power limit and a bus workload comparison). Practitioners may focus on this term because the accused products likely employ highly complex, multi-factor power management algorithms, and the dispute will be whether those algorithms perform the precise steps recited in the claim.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes a "Power Management/Balancing Module 630" that "makes the power balancing decision" (’494 Patent, col. 12:20-22). This could support a broader functional definition.
    • Evidence for a Narrower Interpretation: The claim language itself provides a narrower definition by explicitly requiring the "balancing control" to act based on "a power limit...and a comparison between the bus workload and a bus workload threshold." A defendant may argue that this recitation limits the term to a control system that performs this specific two-factor analysis, as opposed to a more holistic, multi-variable heuristic.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement, stating that Google knowingly encourages consumers to use the Accused Products in their intended, infringing manner by supplying the products and related instructions (Compl. ¶44-45, ¶56-57). The complaint also makes allegations of contributory infringement, asserting the products are a material part of the invention and are not staple articles of commerce (Compl. ¶46, ¶58).
  • Willful Infringement: The willfulness allegations are based on Google’s alleged knowledge of the patents "at least as of the filing of this Complaint" (Compl. ¶49, ¶61). No facts suggesting pre-suit knowledge are alleged.

VII. Analyst’s Conclusion: Key Questions for the Case

  1. A central issue will be one of architectural correspondence: Can the specific processor domains and control logic recited in the patent claims (e.g., a "first domain" of cores, a "second domain" of graphics, and a distinct "communication bus") be mapped onto the complex, heterogeneous architectures of Google's Tensor SOCs and Axion CPUs, which contain additional specialized units like AI accelerators and sophisticated on-chip fabrics?
  2. A key legal question will be one of functional specificity: Will the infringement analysis turn on whether Google's power management systems perform the exact logical steps recited in the claims (e.g., basing a decision on a "comparison between the bus workload and a bus workload threshold" per the '494 patent), or will a more general functional equivalence be sufficient?
  3. A significant procedural factor will be the estoppel effect of prior IPRs: How will the successful defense of the '833 and '494 patents in prior PTAB proceedings limit the scope of invalidity arguments that Google can assert in this litigation, and how might that prior validation influence the parties' strategies regarding claim construction and settlement?