DCT

7:25-cv-00413

Daedalus Prime LLC v. Marvell Technology Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 7:25-cv-00413, W.D. Tex., 09/08/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant maintains multiple regular and established places of business in the district, employs numerous individuals in the district, and has committed acts of infringement in the district.
  • Core Dispute: Plaintiff alleges that Defendant’s microprocessor products, including the Octeon 10 DPU, infringe six patents, originally assigned to Intel Corporation, related to microprocessor power management, cache architecture, and multi-domain power budget allocation.
  • Technical Context: The patents relate to techniques for improving performance and power efficiency in complex multi-core processors, a critical technology for data centers, 5G wireless infrastructure, and enterprise computing applications.
  • Key Procedural History: The complaint notes that U.S. Patent No. 8,775,833 survived an inter partes review (IPR2023-01335), where the Patent Trial and Appeal Board (PTAB) found that the petitioner failed to establish the unpatentability of several claims.

Case Timeline

Date Event
2003-03-03 Marvell first registered to do business in Texas
2011-09-06 Earliest Priority Date for ’316 Patent and ’833 Patent
2011-12-13 Earliest Priority Date for ’228 Patent
2011-12-15 Earliest Priority Date for ’197 Patent
2012-12-28 Earliest Priority Date for ’960 Patent and ’919 Patent
2014-07-01 ’316 Patent Issued
2014-07-08 ’833 Patent Issued
2015-03-17 ’228 Patent Issued
2019-08-06 ’197 Patent Issued
2020-07-07 ’960 Patent Issued
2020-07-28 ’919 Patent Issued
2025-09-08 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 10,372,197 - User Level Control of Power Management Policies

Issued Aug. 6, 2019

The Invention Explained

  • Problem Addressed: The patent describes the difficulty for end-users to optimize the complex power management features of modern processors. While processors offer many tunable features, users rarely venture beyond default settings, leaving potential power savings unrealized, particularly for users willing to trade some performance for efficiency (’197 Patent, col. 2:1-6).
  • The Patented Solution: The invention proposes a simplified, high-level control mechanism called an "energy performance bias" (EPB). A user or operating system can provide a single EPB value that indicates a desired trade-off between power and performance. A power controller within the processor uses this single EPB value, potentially in combination with a "workload configuration input," to consult a tuning table and automatically update settings for a plurality of different power management features, simplifying the optimization process (’197 Patent, col. 2:34-40; Fig. 4). The complaint reproduces Figure 4 from the patent, which illustrates a multicore processor architecture including a power control unit with policy tuning logic (Compl. ¶19).
  • Technical Importance: This approach abstracts away the complexity of tuning dozens of individual hardware settings, making power/performance optimization accessible to non-expert users and automated management systems.

Key Claims at a Glance

  • Independent Claim Asserted: Claim 1
  • Essential Elements of Claim 1:
    • A processor with a plurality of cores, a cache memory, and an interconnect.
    • A power controller that controls multiple power management features.
    • The power controller includes a tuning circuit that:
      • receives a workload configuration input regarding a workload,
      • receives a plurality of energy performance bias (EPB) values,
      • determines a global EPB value based on the received EPB values, and
      • updates at least one setting of at least one power management feature based on both the workload configuration input and the global EPB value.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent (Compl. ¶¶47-49).

U.S. Patent No. 10,705,960 - Processors Having Virtually Clustered Cores and Cache Slices

Issued Jul. 7, 2020

The Invention Explained

  • Problem Addressed: In multi-core processors with a shared, physically distributed cache, the time for a core to access data in a cache slice depends on the physical distance between them. As the number of cores increases, the average access latency also increases, which can degrade performance (’960 Patent, col. 1:36-47).
  • The Patented Solution: The invention logically groups, or "virtually clusters," cores and their corresponding nearby cache slices. When a core needs data not in its local cache, the request is initially directed only to the other cache slices within its virtual cluster, reducing the average distance the request must travel. The patent's Figure 1, reproduced in the complaint, shows a processor with cores and cache slices organized into a "First Virtual Cluster" and a "Second Virtual Cluster" (Compl. ¶24; ’960 Patent, Fig. 1). The invention also discloses power management circuitry that can operate these different clusters at different frequencies and selectively gate power to them, enhancing efficiency (’960 Patent, col. 12:7-24).
  • Technical Importance: Virtual clustering improves performance and efficiency in many-core processors by localizing cache traffic and enabling more granular power control over different regions of the chip.

Key Claims at a Glance

  • Independent Claim Asserted: Claim 1
  • Essential Elements of Claim 1:
    • A system with a plurality of symmetric multi-threaded cores.
    • A cache subsystem with first-level caches and a higher-level distributed cache, with distributed portions shared by and accessible to the cores.
    • Cache management circuitry for coherent, non-uniform access.
    • Power management circuitry that:
      • enables a first frequency for a first cluster of physically proximate cores and a second frequency for a second cluster, where the average distance between cores in the first cluster is less than the average distance between all cores.
      • selectively gates power to the first cluster and its corresponding cache portions, and/or to the second cluster and its corresponding cache portions.
    • First and second integrated memory controllers.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent (Compl. ¶¶59-61).

U.S. Patent No. 10,725,919 - Processors Having Virtually Clustered Cores and Cache Slices

Issued July 28, 2020

  • Technology Synopsis: This patent is related to the ’960 Patent and similarly addresses performance degradation from increased cache access latency in many-core processors. It claims a processor with virtually clustered cores and cache slices, along with power management circuitry to enable different operating frequencies for different clusters and to selectively gate power to them (’919 Patent, Abstract; col. 10:1-18).
  • Asserted Claims: Claim 1 is asserted (Compl. ¶¶71-73).
  • Accused Features: The complaint alleges that Marvell's microprocessor products, including the Octeon 10, infringe by incorporating the claimed processor architecture (Compl. ¶71).

U.S. Patent No. 8,769,316 - Dynamically Allocating a Power Budget Over Multiple Domains of a Processor

Issued July 1, 2014

  • Technology Synopsis: This patent describes a method for managing power in a multi-domain processor (e.g., a processor with separate core and graphics domains). A power controller determines a total power budget and allocates it between a first and second domain, allocating a minimum reservation value to each and sharing the remaining portion according to sharing policy values, then controlling the frequency of each domain based on its allocation (’316 Patent, Abstract; col. 12:12-25).
  • Asserted Claims: Claim 8 is asserted (Compl. ¶¶83-85).
  • Accused Features: The complaint alleges that Marvell's microprocessor products, including the Octeon 10, infringe by practicing the claimed power budget allocation method (Compl. ¶83).

U.S. Patent No. 8,775,833 - Dynamically Allocating a Power Budget Over Multiple Domains of a Processor

Issued July 8, 2014

  • Technology Synopsis: This patent is related to the ’316 Patent and claims a system for dynamic power allocation. It specifies a multicore processor with a first domain (cores), a second domain (graphics), and a third domain (system agent) operating at a fixed power budget. Power sharing logic dynamically allocates a variable power budget between the first and second domains based on stored power sharing values for each (’833 Patent, Abstract; col. 13:51-64).
  • Asserted Claims: The complaint asserts at least Claim 14, which recites a system similar to Claim 13 but omits the DRAM limitation (Compl. ¶¶95-97; ’833 Patent, col. 14:16-32).
  • Accused Features: The complaint alleges that Marvell's microprocessor products, including the Octeon 10, infringe by incorporating the claimed multi-domain power sharing system (Compl. ¶95).

U.S. Patent No. 8,984,228 - Providing Common Caching Agent for Core and Integrated Input/Output (IO) Module

Issued March 17, 2015

  • Technology Synopsis: This patent addresses problems that arise when an Input/Output (IO) component is integrated onto the same chip as a multiprocessor. Instead of treating the IO component as a separate caching agent requiring its own logic, the invention provides a single, common caching agent to perform cache coherency operations for both the processor cores and the integrated IO module, reducing snoop traffic (’228 Patent, col. 1:19-28, 3:8-9).
  • Asserted Claims: Claim 1 is asserted (Compl. ¶¶107-109).
  • Accused Features: The complaint alleges that Marvell's microprocessor products, including the Octeon 10, infringe by incorporating the claimed common caching agent architecture (Compl. ¶107).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies the "Accused Products" as Marvell's microprocessor products, specifically including the "Octeon 10 DPU," and all reasonably similar products (Compl. ¶47, ¶59).

Functionality and Market Context

  • The complaint alleges the Accused Products are semiconductors and processors used in mobile phones and data centers (Compl. ¶8). It includes a product brief for the Marvell® OCTEON 10 DPU Platform, describing it as a "DPU family designed for demanding cloud, 5G wireless, enterprise, carrier and datacenters applications" (Compl. ¶8, p. 3).
  • The product brief screenshot highlights features such as being based on a 5nm Arm Neoverse N2 platform, incorporating hardware acceleration engines, and supporting high-speed I/O interfaces like DDR5 and PCIe 5.0 (Compl. ¶8, p. 3).
  • The complaint alleges the Accused Products are sold, offered for sale, and used in the United States and specifically within the Western District of Texas (Compl. ¶6, ¶9).

IV. Analysis of Infringement Allegations

’197 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A processor comprising: a plurality of cores; a cache memory; an interconnect to couple the plurality of cores and the cache memory; The complaint alleges the Accused Products are multicore processors but does not specify how this element is met. ¶47, ¶49 col. 9:2-5
and a power controller to control a plurality of power management features of the processor, The complaint does not provide sufficient detail for analysis of this element. ¶47, ¶49 col. 9:14-18
wherein the power controller includes a tuning circuit to receive a workload configuration input regarding a workload, The complaint does not provide sufficient detail for analysis of this element. ¶47, ¶49 col. 7:1-5
receive a plurality of energy performance bias (EPB) values and determine a global EPB value based thereon, The complaint does not provide sufficient detail for analysis of this element. ¶47, ¶49 col. 5:5-24
and update at least one setting of at least one of the plurality of power management features based on the workload configuration input and the global EPB value. The complaint does not provide sufficient detail for analysis of this element. ¶47, ¶49 col. 5:60-67

’960 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A system comprising: a plurality of cores, the plurality of cores comprising symmetric multi-threaded cores; The complaint alleges the Accused Products are multicore processors but does not specify how this element is met. ¶59, ¶61 col. 3:20-22
a cache subsystem...comprising a plurality of distributed cache portions that are physically distributed across a die and shared by the plurality of cores... The complaint does not provide sufficient detail for analysis of this element. ¶59, ¶61 col. 4:57-65
cache management circuitry operative to provide coherent, non-uniform access to the plurality of distributed cache portions by the plurality of cores; The complaint does not provide sufficient detail for analysis of this element. ¶59, ¶61 col. 5:12-16
power management circuitry operative to enable a first frequency of operation for a first cluster... and a second frequency of operation for a second cluster... wherein an average distance between cores in the first cluster is less than an average distance between the plurality of cores, The complaint does not provide sufficient detail for analysis of this element. ¶59, ¶61 col. 12:15-23
the power management circuitry operative to selectively gate power to the first cluster...and/or the second cluster... The complaint does not provide sufficient detail for analysis of this element. ¶59, ¶61 col. 12:35-43
a first integrated memory controller coupled with the symmetric multi-threaded cores; and a second integrated memory controller... The complaint does not provide sufficient detail for analysis of this element. ¶59, ¶61 col. 3:14-18
  • Identified Points of Contention:
    • Evidentiary Questions: The complaint makes broad allegations that the Accused Products infringe but does not map specific features of the Octeon 10 DPU (or any other product) to the elements of the asserted claims. A central point of contention will be whether Plaintiff can produce evidence that the accused processors actually perform the specific functions required by each claim limitation, such as receiving "EPB values," determining a "global EPB value," or organizing cores into "virtual clusters" that are managed by "power management circuitry" in the claimed manner.
    • Scope Questions: For the ’197 Patent, a question may arise as to what constitutes a "workload configuration input" and a "plurality of energy performance bias (EPB) values." The analysis will depend on whether the accused Octeon 10 processors receive inputs that correspond in structure and function to those described in the patent specification. For the ’960 Patent, a key question will be whether the accused processors organize their cores into "clusters" and employ power management circuitry that operates on these clusters in the specific manner recited by the claim, including enabling different frequencies and selectively gating power based on cluster organization.

V. Key Claim Terms for Construction

For the ’197 Patent:

  • The Term: "workload configuration input"
  • Context and Importance: This input is a distinct element from the "EPB values" and is used, along with the global EPB value, to update power settings. The scope of this term is critical because if it is construed narrowly to require a specific type of user-defined input (e.g., "NUMA" or "I/O intensive"), it may be more difficult to prove infringement than if it is construed broadly to cover any system-generated signal related to workload type.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language itself is broad, referring simply to "a workload configuration input regarding a workload" (’197 Patent, col. 12:4).
    • Evidence for a Narrower Interpretation: The specification provides specific examples, stating a user can configure the input as "non-uniform memory architecture (NUMA), uniform memory architecture (UMA), input/output (I/O) intensive, etc." (’197 Patent, col. 7:3-6). This suggests the input may be a user- or administrator-level selection from a predefined set of workload types.

For the ’960 Patent:

  • The Term: "cluster of the plurality of cores which are physically proximate to one another"
  • Context and Importance: The claim requires power management circuitry to operate on these defined "clusters." The definition of a "cluster" and the standard for "physically proximate" will be central to determining if the accused processor architecture meets this limitation. Practitioners may focus on this term because the defendant could argue its architecture groups cores based on a different logic (e.g., functional units, not just physical proximity) or that its definition of proximity does not align with the patent's.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent describes grouping as potentially being based on "physical proximity" or being on the "same ring interconnect or other interconnect structure" (’960 Patent, col. 6:58-60, col. 6:6-9), which could support a range of physical arrangements being considered a "cluster."
    • Evidence for a Narrower Interpretation: The claim requires a specific mathematical relationship: "an average distance between cores in the first cluster is less than an average distance between the plurality of cores" (’960 Patent, col. 25:11-13). This provides a specific, measurable constraint that could narrow the scope of what qualifies as a "cluster." The patent also consistently uses the term "virtual cluster" throughout the specification, which may inform the interpretation of "cluster" in the claim (’960 Patent, col. 5:30-47).

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement for all asserted patents. It claims Marvell knowingly induces infringement by supplying the Accused Products to consumers and "instructing and encouraging" them to use the products in their "ordinary, customary, and intended way," which Marvell allegedly knew was infringing (Compl. ¶49, ¶61, ¶73, ¶85, ¶97, ¶109). The complaint does not cite specific user manuals, marketing materials, or other instructional documents.
  • Willful Infringement: The complaint alleges willful infringement for all asserted patents. The basis for willfulness is Marvell's alleged knowledge of the patents "at a minimum, as of the filing of this Complaint" (Compl. ¶54, ¶66, ¶78, ¶90, ¶102, ¶114). This suggests the willfulness claim is based on post-suit conduct.

VII. Analyst’s Conclusion: Key Questions for the Case

  1. Evidentiary Sufficiency: A primary issue will be whether the Plaintiff can move beyond the complaint's conclusory allegations and produce technical evidence—such as source code, chip schematics, or expert testimony—that demonstrates the accused Marvell Octeon 10 DPU processors actually implement the specific architectures and methods required by the asserted claims. The lack of detailed factual allegations in the complaint places the evidentiary burden squarely on discovery.
  2. Architectural Correspondence: The case will likely turn on a question of technical mapping: do the methods by which Marvell's processors manage power, cache, and I/O operations correspond to the specific claimed inventions? For example, does the Octeon 10 use a "global EPB value" derived from multiple other values to consult a tuning table as claimed in the ’197 Patent, or does it use a different power management logic? Similarly, does it organize its cores into "virtual clusters" with dedicated power gating and frequency control as required by the ’960 and ’919 Patents?
  3. Claim Scope and Construction: A central legal question will involve definitional scope, particularly for terms like "workload configuration input" (’197 Patent) and "cluster of...cores which are physically proximate" (’960 Patent). The outcome of claim construction for these terms will significantly influence whether the operational realities of the accused products fall within the bounds of the patent claims.