DCT

7:25-cv-00415

HFT Solutions LLC v. Optiver US LLC

I. Executive Summary and Procedural Information

Parties & Counsel:
- Plaintiff: HFT Solutions LLC (Delaware)
- Defendant: Optiver US LLC and Optiver Trading US LLC (Illinois)
- Plaintiff’s Counsel: Russ August & Kabat
Case Identification: 7:25-cv-00415, W.D. Tex., 09/08/2025
Venue Allegations: Plaintiff alleges venue is proper because Defendants have a regular and established place of business within the Western District of Texas.
Core Dispute: Plaintiff alleges that Defendant’s high-frequency trading platforms, which utilize Field-Programmable Gate Arrays (FPGAs), infringe three patents related to reducing processing latency by synchronizing internal clock signals via an external phase-locked loop.
Technical Context: The technology addresses the critical need for minimizing processing delays in FPGAs, a key performance metric for latency-sensitive applications like high-frequency trading where nanosecond advantages can be significant.
Key Procedural History: The complaint does not reference any prior litigation, inter partes review proceedings, or licensing history concerning the patents-in-suit. The asserted patents are all members of the same patent family.

Case Timeline

Date	Event
2018-11-05	Priority Date for ’286, ’305, and ’381 Patents
2021-02-23	’286 Patent Issued
2021-02-23	Alleged Infringement Begins
2021-09-21	’305 Patent Issued
2023-02-07	’381 Patent Issued
2025-09-08	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 10,931,286 - Field programmable gate array with external phase-locked loop

The Invention Explained

Problem Addressed: The patent’s background section describes a technical problem in conventional Field-Programmable Gate Arrays (FPGAs) where synchronizing the internal receiver-side and transmitter-side clock signals requires a "clock domain crossing circuit." This circuit, however, inherently introduces processing delays, or latency, which is undesirable in high-speed applications like high-frequency trading (’286 Patent, col. 1:36-54).
The Patented Solution: The invention proposes removing the phase-matching function from the FPGA chip to an external circuit. The system is designed to output both the receiver-side clock and the transmitter-side clock from the FPGA to an external phase detector. This detector compares the phases of the two clocks and, via a controller, adjusts an external oscillator that provides the reference clock for the transmitter side. This external feedback loop aligns the phases of the internal clocks, obviating the need for the latency-inducing internal clock domain crossing circuit (’286 Patent, Fig. 2; col. 2:59-col. 3:20).
Technical Importance: This architecture directly addresses the market demand for sub-microsecond processing in FPGAs by seeking to eliminate a known source of latency, which is a critical performance bottleneck in fields like high-frequency financial trading (Compl. ¶7; ’286 Patent, col. 1:47-54).

Key Claims at a Glance

The complaint asserts independent claim 1 and reserves the right to assert other claims, including dependent claims.
The essential elements of independent claim 1, a method claim, include:
- Receiving a first serial data stream and a first clock signal at an FPGA.
- Generating a first receiver-side clock signal within the FPGA based on the first clock signal.
- Transmitting the first receiver-side clock signal from the FPGA via a first clock output pin to an external phase detector.
- Generating a first transmitter-side clock signal, which involves a multi-step feedback loop performed until a phase detector output is below a threshold. This loop includes:
  - Generating a second clock signal via an external adjustable oscillator.
  - Generating an output from the phase detector based on comparing the receiver-side clock signal and a feedback clock signal derived from the second clock signal.
  - Transmitting this output to an external phase controller, which determines adjustment information.
  - Transmitting the adjustment information to the adjustable oscillator to adjust the second clock signal.
- Generating, by a serializer in the FPGA, the first transmitter-side clock signal based on the second clock signal.
- Performing a set of operations on the data within the FPGA's computational circuitry.
- Converting the resulting parallel data into a second serial data stream using the serializer.
- Transmitting the second serial data stream from the FPGA.

U.S. Patent No. 11,128,305 - Field programmable gate array with external phase-locked loop

The Invention Explained

The technology disclosed in the ’305 Patent is substantively identical to that of the ’286 Patent, as described above. Both patents share the same specification and figures, originating from the same chain of patent applications (’305 Patent, col. 1:7-22). The core technical problem and patented solution are the same.

Key Claims at a Glance

The complaint asserts independent claim 1 and reserves the right to assert other claims.
The essential elements of independent claim 1, a system claim, include:
- An FPGA comprising a first interface (with reference clock and data pins), a deserializer, computational circuitry, and a serializer.
- A second interface on the FPGA with clock output pins for the receiver-side and transmitter-side clocks.
- A phase control circuit, provided outside of the FPGA, which comprises:
  - A phase detector connected to the clock output pins to compare the phases of the receiver and transmitter clocks.
  - A phase controller to determine adjustment information based on the phase difference.
  - An adjustable oscillator, connected to the phase controller and the FPGA's second reference clock pin, to generate an adjusted clock signal based on the adjustment information.
- The system is configured such that the transmitter-side and receiver-side clock signals become phase-aligned.

U.S. Patent No. 11,575,381 - Field programmable gate array with external phase-locked loop

Technology Synopsis: This patent, from the same family as the ’286 and ’305 patents, describes a method and system for reducing processing latency in an FPGA by using an external phase controller to synchronize the receiver-side and transmitter-side clocks, thereby avoiding the need for an internal clock domain crossing circuit (Compl. ¶¶44-45; ’381 Patent, col. 1:45-col. 2:4).
Asserted Claims: Independent claim 1 is asserted (Compl. ¶48).
Accused Features: The complaint alleges that Optiver's high-frequency trading platforms, which use FPGAs to achieve low-latency trade execution, practice the patented method (Compl. ¶¶ 7-9, 46, 48).

III. The Accused Instrumentality

Product Identification

The Accused Instrumentalities are FPGA systems and platforms used by Defendants for high-frequency trading strategies (Compl. ¶¶ 7-8). Specific hardware identified includes platforms incorporating Bittware XUP-VV8 and AMD Alveo U55C, UL3524, and UL3422 FPGA boards (Compl. ¶8).

Functionality and Market Context

The complaint alleges that Defendants configure and use these FPGA platforms to achieve competitive trading speeds, which are critical for success in high-frequency trading (Compl. ¶¶ 7, 9). The alleged functionality involves placing trading logic as close as possible to the network interface within the FPGA to "cut away all the extra overhead, latency, of PCI express and our software application and CPU and memory problems" (Compl. ¶9). The complaint further alleges that Defendants' infringement provides benefits such as higher success rates and increased profits in latency-sensitive trades (Compl. ¶24).
No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

’286 Patent Infringement Allegations

The complaint alleges that Defendants' use of the Accused Instrumentalities infringes claim 1 of the ’286 Patent (Compl. ¶22). The pleading states that the basis for this infringement is "shown in Exhibit 4 which is incorporated herein by reference" (Compl. ¶22). As this exhibit was not provided with the complaint, the complaint does not provide sufficient detail for a claim-by-claim analysis of the infringement allegations.

’305 Patent Infringement Allegations

The complaint alleges that the Accused Instrumentalities infringe claim 1 of the ’305 Patent (Compl. ¶35). The pleading states that the basis for this infringement is "shown in Exhibit 5," which is incorporated by reference but was not provided with the complaint (Compl. ¶35). Accordingly, the complaint does not provide sufficient detail for a claim-by-claim analysis of the infringement allegations.

Identified Points of Contention

Architectural Questions: The claims require a specific architecture where receiver and transmitter clock signals are physically output from the FPGA for comparison by an external circuit, which in turn controls an external oscillator that feeds the transmitter's clock input. A central question will be whether discovery reveals that the accused FPGA platforms actually implement this external feedback loop, or if they achieve low latency through other, non-infringing methods, such as advanced on-chip clock management resources common in modern FPGAs.
Scope Questions: The claims recite a "phase control circuit, provided outside of the field programmable gate array." The dispute may involve whether the various components of the accused trading platforms (e.g., FPGA boards, host systems, other connected hardware) constitute such an "outside" circuit that performs the claimed functions, or if all relevant phase management is performed by components considered integral to the FPGA system itself.

V. Key Claim Terms for Construction

The Term: "phase control circuit, provided outside of the field programmable gate array" (’305 Patent, cl. 1)

Context and Importance: This term is central to the point of novelty, which is moving the clock synchronization function "outside" the FPGA to avoid internal latency. The definition of what constitutes "outside of the field programmable gate array" will be critical. A defendant may argue that components on the same printed circuit board as the FPGA chip are part of the "array system" and therefore not "outside" of it, while the plaintiff may argue "gate array" refers narrowly to the chip itself.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes the "phase control circuit" as including a phase detector, a phase controller, and an adjustable oscillator, without limiting them to a single physical housing (’305 Patent, col. 3:1-20). This could support a construction where any collection of off-chip components performing these roles meets the limitation.
- Evidence for a Narrower Interpretation: Figure 2 depicts the FPGA (2100) and the external control components (2200, 2202, 2206) as distinct blocks connected via an "External Connection" (2122). A party could argue this drawing limits the term to a configuration where the control circuit is physically and electrically distinct from the main FPGA board.

The Term: "transmitting, from the deserializer via a first clock output pin...the first receiver side clock signal" (’286 Patent, cl. 1)

Context and Importance: This claim element requires the FPGA to physically export its internally-generated receiver-side clock for use by the external phase detector. Infringement analysis will depend on whether the accused systems are technically configured to output this specific clock signal on a dedicated or general-purpose pin for this purpose. Practitioners may focus on this term because it defines a specific I/O behavior required to enable the external feedback loop.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim language recites "a first clock output pin," which could be interpreted to mean any pin on the FPGA capable of outputting a clock signal, suggesting flexibility in implementation (’286 Patent, col. 28:34-38).
- Evidence for a Narrower Interpretation: The specification describes the system's operation as a direct comparison between the receiver and transmitter clocks to generate a phase difference signal (’286 Patent, col. 3:1-8). This may support a narrower construction requiring that the signal on the output pin is a direct, unmodified representation of the internal receiver-side clock, rather than a processed or encoded signal from which a clock could be derived.

VI. Other Allegations

Willful Infringement: The complaint alleges that infringement has been and continues to be willful based on Defendants' knowledge of the patents "since at least service of this Complaint" (Compl. ¶¶ 23, 36, 49). This is an allegation of post-suit willfulness.

VII. Analyst’s Conclusion: Key Questions for the Case

A core issue will be one of architectural identity: Do the accused high-frequency trading platforms, built on sophisticated commercial FPGA boards, actually implement the specific external phase-locked loop architecture required by the claims? The case will likely depend on evidence showing whether the systems physically output internal receiver and transmitter clock signals for comparison by an off-FPGA circuit that, in turn, adjusts an external oscillator to achieve phase alignment.
A key evidentiary question will be one of technical operation: Given the complaint's reliance on high-level marketing materials and unprovided technical exhibits, the dispute will turn on whether discovery reveals that the accused products' low-latency functionality operates in the specific manner recited in the claims, or through alternative, non-infringing methods such as advanced on-chip clock management, proprietary IP cores, or different software/hardware co-design techniques.