DCT

7:25-cv-00455

Edgecomm LLC v. Marvell Semiconductor Inc

Log In
Key Events
Complaint

I. Executive Summary and Procedural Information

Case Timeline

Date Event
2007-02-02 ’279 Patent - Earliest Priority Date
2008-02-04 ’483 Patent - Earliest Priority Date
2012-07-31 ’483 Patent - Issue Date
2018-04-10 ’279 Patent - Issue Date
2025-10-07 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,234,483 - "Memory units with packet processor for decapsulating read write access from and encapsulating response to external devices via serial packet switched protocol interface," issued July 31, 2012 (’483 Patent)

The Invention Explained

  • Problem Addressed: The patent's background describes the "memory wall problem," where the increasing speed of processors outpaces the speed of memory access over traditional parallel bus architectures, creating a performance bottleneck. These parallel buses are also described as being prone to "clock skew" and consuming "considerable circuit board real estate." (’483 Patent, col. 2:15-24, col. 2:59-67).
  • The Patented Solution: The invention proposes an architecture where memory chips are equipped with their own integrated "packet processor." This processor manages communication over a high-speed serial interface, such as Ethernet. It receives memory access commands (e.g., read/write) from an external device like a CPU, decapsulates these commands from incoming data packets, and encapsulates the resulting data into new packets for transmission back to the external device. (’483 Patent, Abstract; col. 11:31-50). This structure moves the communication logic onto the memory die itself, replacing the conventional shared parallel bus with a point-to-point serial link.
  • Technical Importance: This architecture aimed to alleviate the physical and electrical constraints of parallel buses, allowing for faster and more scalable communication between processors and memory components. (’483 Patent, col. 4:49-56).

Key Claims at a Glance

  • The complaint asserts infringement of one or more unspecified claims of the ’483 Patent (Compl. ¶12). Independent claim 1 is representative:
    • An apparatus comprising at least one memory device and at least one packet processor uniquely associated with it.
    • The packet processor is adapted to provide an external device read/write access to the memory device via a high-speed packet switched serial interface.
    • This is achieved by decapsulating address, data, and control information from a received packet conforming to a predefined serial protocol.
    • It further involves encapsulating data, including the decapsulated address and control information, into another packet for transmission in response.
    • The memory device and its associated packet processor are co-located on a single semiconductor die package with an external port for the serial interface.

U.S. Patent No. 9,940,279 - "Processor apparatus with programmable multi port serial communication interconnections," issued April 10, 2018 (’279 Patent)

The Invention Explained

  • Problem Addressed: The patent addresses the architectural limitations of conventional computer systems where a central bus (like the Front Side Bus) acts as a chokepoint for all communications between the CPU, memory, and I/O devices. This is inefficient as processor, memory, and network speeds continue to increase. (’279 Patent, col. 2:50-62).
  • The Patented Solution: The invention describes a processor apparatus built on a single semiconductor die that contains multiple processor cores and an integrated, programmable multi-port switch. This switch acts as an on-chip communications hub, providing multiple high-speed serial ports. It is designed to handle various packetized serial protocols (e.g., Ethernet, PCI Express) and can provide "translation between multiple serialized protocols." (’279 Patent, Abstract; col. 12:59-62). This allows processor cores to communicate directly with different external devices over dedicated serial links using the appropriate protocol, bypassing a central bus. (’279 Patent, Fig. 2C).
  • Technical Importance: This design offers a flexible and scalable on-chip networking solution, enabling more efficient data routing for multi-core processors that must interface with a diverse and growing number of high-speed peripherals and networks. (’279 Patent, col. 10:1-17).

Key Claims at a Glance

  • The complaint asserts infringement of one or more unspecified claims of the ’279 Patent (Compl. ¶21). Independent claim 1 is representative:
    • An apparatus comprising at least a pair of processor cores, a pair of external ports, and at least one switch, all collocated on a semiconductor die package.
    • The switch operably connects the processor cores and the external ports.
    • The processor cores are adapted to communicate with external devices using packetized serial communication.
    • The switch is adapted for packetized serial communication among the cores and ports.
    • Crucially, the switch is adapted to provide "translation between multiple serialized protocols."
    • Each external port is adapted to provide a predefined serial communications interface.

III. The Accused Instrumentality

Product Identification

  • The complaint accuses "Exemplary Defendant Products" made, used, sold, or imported by Marvell Semiconductor, Inc. (Compl. ¶12, ¶21).

Functionality and Market Context

  • The complaint incorporates by reference Exhibits 3 and 4, which allegedly contain claim charts identifying the accused products and detailing their infringing functionality (Compl. ¶17, ¶26). As these exhibits are not included with the complaint, the specific products and their technical operations are not described in the provided document. The allegations suggest the accused products are semiconductor devices that practice the claimed on-chip serial communication architectures.
  • No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint does not contain claim charts or detailed infringement allegations in its body, instead incorporating them by reference to Exhibits 3 and 4, which were not provided (Compl. ¶18, ¶27). The narrative infringement theory alleges that the "Exemplary Defendant Products" practice the technology claimed by the Patents-in-Suit and satisfy all elements of the asserted claims (Compl. ¶17, ¶26). Without the exhibits, a detailed element-by-element analysis is not possible.

  • Identified Points of Contention:
    • Architectural Questions (’483 Patent): A potential area of dispute may be whether the accused products contain a "packet processor" that is "uniquely associated with" a memory device on the same die, as required by the claim. The defense may argue its architecture is different, for example, using a more general-purpose interconnect or a processor that is not uniquely tied to a specific memory element.
    • Functional Questions (’279 Patent): The analysis may turn on the meaning and function of the claimed "switch." Key questions could be whether the accused device's switch is "programmable" in the manner contemplated by the patent and, critically, whether it performs "translation between multiple serialized protocols." An accused device that merely routes different protocols without actively translating between them may fall outside the claim scope.

V. Key Claim Terms for Construction

For the ’483 Patent:

  • The Term: "packet processor uniquely associated with each of the at least one memory device" (Claim 1)
  • Context and Importance: This term is central to defining the required relationship between the processing and memory components. The nature of this "unique association" will likely determine whether a defendant's integrated, multi-function communication fabric infringes a claim that appears to require a more dedicated, one-to-one link.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification does not explicitly define "uniquely associated." A party could argue it simply means the packet processor is the designated component for handling serial packet communications for that memory device, without precluding other functions.
    • Evidence for a Narrower Interpretation: The phrasing "uniquely associated with each" suggests a tight, potentially exclusive, pairing. The patent's abstract and claims emphasize the packet processor's role in encapsulating and decapsulating for a specific memory device, which may support an interpretation that the processor's primary function is to serve that memory element. (’483 Patent, Abstract; col. 11:31-35).

For the ’279 Patent:

  • The Term: "switch is adopted to provide translation between multiple serialized protocols" (Claim 1)
  • Context and Importance: This limitation appears to require more than simple routing. The case may depend on whether the accused switch performs active protocol conversion. Practitioners may focus on this term because many modern switches can route traffic from different protocols (e.g., Ethernet, PCIe) without necessarily reformatting the data packets from one protocol standard to another.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: A party might argue that "translation" could broadly encompass any logic that allows disparate protocols to coexist and interoperate through the switch, even if it is just intelligent routing.
    • Evidence for a Narrower Interpretation: The specification describes a "Bit Stream processor" that performs a "forward and reverse bridging function" and can be programmed to handle different protocols, suggesting an active conversion process. It notes the processor bridges "between the intra-processor protocol and one of a set of board-level or network level serial communication protocols." (’279 Patent, col. 9:18-29). This language supports a construction requiring active reformatting of packet headers or data structures from one protocol to another.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement for both patents. It claims Defendant distributes "product literature and website materials" that instruct and encourage end users to use the accused products in an infringing manner (Compl. ¶15-16, ¶24-25).
  • Willful Infringement: Willfulness allegations for both patents are based on alleged knowledge of infringement acquired "[a]t least since being served by this Complaint." This frames the claim as one of post-filing willfulness (Compl. ¶14, ¶16, ¶23, ¶25).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. Architectural Mapping: A core issue will be one of structural correspondence: does the specific on-die architecture of Marvell's accused products map directly onto the claimed arrangement of a "packet processor uniquely associated with" a memory device (’483 Patent), or a "programmable switch" connecting cores and ports (’279 Patent), or does it employ a fundamentally different, non-infringing design?

  2. Functional Scope of "Translation": The dispute over the ’279 Patent may hinge on a question of technical function: does the term "translation between multiple serialized protocols" require active packet reformatting and protocol conversion, or can it be read more broadly to cover a switch that intelligently routes traffic from different, coexisting serial protocols?

  3. Evidentiary Sufficiency: Since the complaint's technical infringement details are confined to un-provided exhibits, a primary challenge for the plaintiff will be to develop an evidentiary record through discovery that demonstrates the accused semiconductor devices actually perform the specific claimed functions of decapsulating/encapsulating memory commands into serial packets and/or translating between distinct serial protocols.