DCT

7:25-cv-00456

Edgecomm LLC v. NVIDIA Corp

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 7:25-cv-00456, W.D. Tex., 10/07/2025
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant maintains an established place of business within the Western District of Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s processor products infringe three patents related to on-chip architectures that use high-speed, packet-switched serial interfaces to manage communication between processor cores, memory, and external devices.
  • Technical Context: The technology addresses performance bottlenecks in computer architecture by replacing traditional parallel data buses with more efficient integrated serial communication fabrics, a key innovation for scaling performance in multi-core processors and high-performance computing.
  • Key Procedural History: The asserted patents are part of a family stemming from a 2008 priority application. The complaint does not mention any prior litigation, licensing history, or post-grant proceedings involving the patents-in-suit.

Case Timeline

Date Event
2008-02-04 Earliest Priority Date for '483, '688, and '279 Patents
2010-10-25 '483 Patent Application Filed
2012-07-08 '688 Patent Application Filed
2012-07-31 '483 Patent Issued
2014-11-24 '279 Patent Application Filed
2014-12-30 '688 Patent Issued
2018-04-10 '279 Patent Issued
2025-10-07 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,234,483 - "Memory units with packet processor for decapsulating read write access from and encapsulating response to external devices via serial packet switched protocol interface," issued July 31, 2012

  • The Invention Explained:
    • Problem Addressed: The patent’s background section describes the increasing performance gap between fast processors and the slower parallel bus architectures (like the Front-Side Bus) used to access memory, a problem often termed the "Von Neuman Bottleneck." These parallel buses are prone to issues like clock skew and consume significant circuit board space, limiting overall system speed. (’483 Patent, col. 2:10-67).
    • The Patented Solution: The invention proposes an architecture where a "packet processor" is co-located with a memory device on the same semiconductor die. This processor manages communication over a high-speed serial interface. It works by "encapsulating" memory access commands (e.g., address, read/write instructions) into data packets for transmission to an external device and "decapsulating" received packets to execute memory operations. (’483 Patent, Abstract; col. 5:1-14). Figure 5B illustrates a memory chip package (70) containing a dedicated "Parallel Bus to Serial Interface Converter" (100) that performs this function.
    • Technical Importance: This architecture aimed to overcome the physical and electrical limitations of parallel buses, enabling faster, more scalable, and more efficient communication between processors and memory in high-performance computing systems. (’483 Patent, col. 4:51-62).
  • Key Claims at a Glance:
    • The complaint asserts "exemplary claims" without specifying claim numbers (Compl. ¶13). Independent claim 1 is representative of the apparatus claimed.
    • Essential Elements of Claim 1:
      • An apparatus comprising at least one memory device and at least one packet processor "uniquely associated" with each memory device.
      • The packet processor is adapted to provide read/write access to the memory device via a "high-speed packet switched serial interface."
      • The packet processor performs this by decapsulating information from a received packet and encapsulating data into a new packet for transmission.
      • The memory device and packet processor are "co-located on a semiconductor die package" that has an external port for the serial interface.

U.S. Patent No. 8,924,688 - "Plural processing cores communicating packets with external port via parallel bus to serial converter and switch with protocol translation and QOS," issued December 30, 2014

  • The Invention Explained:
    • Problem Addressed: The patent addresses the challenge of managing data flow efficiently in multi-core processor environments, where multiple processing units must share access to memory and I/O devices without creating performance-degrading data traffic jams. (’688 Patent, col. 4:51-57).
    • The Patented Solution: The invention describes a multi-core processor architecture where the cores, an external port, and a "switch" are all integrated onto a single semiconductor die. The switch acts as an intelligent traffic manager, using packetized serial communication to route data between the cores and the external port. Crucially, the switch is described as being able to provide "translation between multiple serialized protocols" and "quality of service (QoS) switching," allowing it to handle different types of data traffic and prioritize critical communications. (’688 Patent, Abstract; col. 8:36-50).
    • Technical Importance: This on-die switching fabric provides a scalable solution for high-performance multi-core processors, enabling efficient communication and preventing the contention issues that would arise with simpler shared-bus architectures. (’688 Patent, col. 7:44-50).
  • Key Claims at a Glance:
    • The complaint asserts "exemplary claims" without specifying claim numbers (Compl. ¶22). Independent claim 1 is representative.
    • Essential Elements of Claim 1:
      • An apparatus comprising a plurality of processor cores, an external port, and at least one switch, all "collocated on the semiconductor die package."
      • The switch is operably connected to the processor cores and the external port.
      • Each processor core sends and receives serial communication protocol data packets via a parallel bus to a programmable serial interface converter.
      • The switch is adapted for packetized serial communication among the cores and the external port.
      • The switch is adapted to provide "translation between multiple serialized protocols."
      • The switch is adapted to provide "quality of service switching."

U.S. Patent No. 9,940,279 - "Processor apparatus with programmable multi port serial communication interconnections," issued April 10, 2018 (Multi-Patent Capsule)

  • Technology Synopsis: This patent extends the concepts of the '688 patent to an apparatus with a pair of processor cores and a pair of external ports. The invention centers on an on-die switch that connects the cores to the ports and is programmable to translate between different serial communication protocols (e.g., PCI Express, Ethernet), enabling flexible, high-speed connections to a variety of external devices or memory systems. (’279 Patent, Abstract; col. 9:1-20).
  • Asserted Claims: The complaint asserts "exemplary claims" without specifying claim numbers (Compl. ¶31). Independent claim 1 is representative.
  • Accused Features: The complaint alleges infringement by Defendant’s products that incorporate multi-core processors with programmable, multi-protocol serial communication interfaces. (Compl. ¶¶31, 36).

III. The Accused Instrumentality

  • Product Identification: The complaint does not identify any specific accused Nvidia products, services, or methods by name. It refers generally to "Exemplary Defendant Products" that are detailed in claim chart exhibits incorporated by reference. (Compl. ¶¶13, 22, 31).
  • Functionality and Market Context: The complaint alleges that the accused products practice the patented technologies, which suggests they are semiconductor devices, such as GPUs or SoCs, containing multiple processor cores that utilize high-speed, on-chip serial interconnects to communicate with each other and with external components like system memory. (Compl. ¶¶18, 27, 36). The complaint does not provide sufficient detail for analysis of the specific functionality or market context of any accused product.

IV. Analysis of Infringement Allegations

The complaint incorporates its infringement allegations by reference to claim chart Exhibits 4, 5, and 6, which were not filed with the public complaint. (Compl. ¶¶19, 28, 37). The complaint’s narrative theory is that Defendant's "Exemplary Defendant Products" practice the technology claimed in the patents-in-suit and therefore satisfy all elements of the asserted claims. (Compl. ¶¶18, 27, 36). Without the claim charts or identification of specific products, a detailed element-by-element analysis is not possible based on the provided documents.

No probative visual evidence provided in complaint.

  • Identified Points of Contention:
    • Scope Questions: A likely point of contention for the ’483 Patent will be the interpretation of a "packet processor uniquely associated with" a memory device. The dispute may turn on whether this requires a distinct, one-to-one hardware component for each memory unit, or if a more integrated memory controller that serves multiple memory banks falls within the claim's scope.
    • Technical Questions: For the ’688 Patent, a central technical question will be whether the accused products’ on-chip interconnects perform the specific functions of "translation between multiple serialized protocols" and "quality of service switching." The case may require evidence demonstrating that the accused switch does more than simply route a single, proprietary protocol and actively manages traffic based on QoS parameters as claimed.

V. Key Claim Terms for Construction

'483 Patent, Claim 1

  • The Term: "packet processor uniquely associated with each of the at least one memory device"
  • Context and Importance: The definition of this term is critical for determining the claimed invention's structure. Whether infringement exists may depend on if Nvidia's memory controller architecture maps onto this "uniquely associated" structure, or if its functionality is organized in a way that avoids this limitation.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the packet processor's function as mediating communications and processing packets for memory access, which could support a functional definition not tied to a strict one-to-one physical structure. (’483 Patent, col. 8:41-54).
    • Evidence for a Narrower Interpretation: The claim language "uniquely associated with each" suggests a direct, singular relationship. Figure 5B depicts a distinct "Memory Chip Package" (70) containing its own "Parallel Bus to Serial Interface Converter" (100), which could be argued as the claimed "packet processor" that is distinct from the main processor package. (’483 Patent, Fig. 5B).

'688 Patent, Claim 1

  • The Term: "switch... adopted to provide translation between multiple serialized protocols"
  • Context and Importance: This term is central to the infringement analysis, as it requires a specific, advanced capability. The dispute will likely focus on whether Nvidia's on-chip fabric (e.g., NVLink) is merely a high-speed router for a proprietary protocol or if it performs genuine "translation" between different industry-standard protocols as contemplated by the patent.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification discloses that the architecture can bridge to numerous standard protocols, including "PCI-Express, 10 Gigabit Ethernet, Infiniband, Advanced Switching, RapidIO," suggesting the invention is meant to cover versatile protocol conversion. (’688 Patent, col. 9:43-49).
    • Evidence for a Narrower Interpretation: A defendant may argue that "translation" requires more than simple packet formatting and entails substantive conversion between distinct, standardized communication languages. The patent's reference to a "programmable pipelined architecture that provides high degree of flexibility for adaptation to legacy, existing and emerging... protocols" could be used to argue that the claimed "translation" is a highly sophisticated and adaptable function. (’688 Patent, col. 9:5-9).

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement, stating that Defendant distributes "product literature and website materials" that instruct customers and end users to operate the accused products in a manner that infringes the patents-in-suit. (Compl. ¶¶16, 26, 35).
  • Willful Infringement: The complaint alleges that Defendant has actual knowledge of its infringement at least from the date of service of the complaint and associated claim charts. The willfulness allegation is based on alleged post-suit conduct. (Compl. ¶¶15, 24, 33).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. Architectural Mapping: A core issue will be one of structural correspondence: can the functional blocks within Nvidia's processor architecture be mapped directly onto the specific "packet processor" and "switch" limitations recited in the claims, or does Nvidia's architecture represent a fundamentally different, non-infringing design?
  2. Evidentiary Proof of Function: The case will likely turn on an evidentiary question of technical capability: what proof can Plaintiff offer that the accused on-chip interconnects perform the advanced functions of "quality of service switching" and "translation between multiple serialized protocols," as required by the '688 patent claims, beyond merely routing high-speed data?
  3. Pleading Sufficiency: A potential threshold issue is the specificity of the infringement allegations. The complaint’s failure to identify a single accused product by name and its reliance on unfiled exhibits may present an early challenge for the defendant regarding whether the allegations meet the plausibility standard required for patent complaints.