DCT

7:25-cv-00458

Wecrevention Inc v. Apple Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 7:25-cv-00458, W.D. Tex., 10/07/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant Apple has regular and established places of business within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s iPhones, MacBooks, and iPads incorporating LPDDR5 DRAM infringe five patents related to reconfigurable memory module architecture and low-power dynamic random access memory (DRAM) operation.
  • Technical Context: The patents relate to memory system architecture and power management, technologies critical to balancing performance and energy efficiency in modern, battery-powered consumer electronics.
  • Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date Event
2011-10-11 Priority Date for ’834 and ’942 Patents
2012-07-17 Priority Date for ’017, ’098, and ’652 Patents
2015-10-20 ’942 Patent Issued
2015-12-01 ’834 Patent Issued
2019-09-01 Alleged Infringement Begins with LPDDR5 Products
2021-05-04 ’017 Patent Issued
2024-02-06 ’098 Patent Issued
2024-11-26 ’652 Patent Issued
2025-10-07 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,201,834 - “Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module,” Issued December 1, 2015

The Invention Explained

  • Problem Addressed: The patent’s background describes that memories are often designed as standard, general-purpose modules, which are not optimized for the specific logic units they connect to. This mismatch can lead to inefficiencies in power consumption, heat dissipation, and noise interference, particularly as the semiconductor manufacturing processes for memory and logic chips diverge (’942 Patent, col. 1:26-51).
  • The Patented Solution: The invention proposes a memory system with programmable interfaces. It describes a "logic unit" that mediates between a group of memory chips and an application-specific integrated circuit (ASIC) processor. The data buses connecting these components have characteristics—such as data rate and signal voltage swing—that can be reconfigured through firmware or software, allowing the interfaces to be optimized for performance and power efficiency (’834 Patent, Abstract; col. 4:54-67). Figure 1 of the patent illustrates the distinct blocks of the memory array group, logic unit, and ASIC processor (’834 Patent, Fig. 1).
  • Technical Importance: This reconfigurability allows a memory subsystem to be dynamically tuned for different processors or operating conditions, improving performance and power efficiency in complex systems-on-chip (’834 Patent, col. 2:20-41).

Key Claims at a Glance

  • The complaint asserts independent claim 21 (Compl. ¶19).
  • The essential elements of claim 21 include:
    • An application-specific integrated circuit (ASIC) processor.
    • A memory cell array group comprising multiple memory cell array ICs.
    • A first transmission bus coupling the memory group, having a first programmable data rate and signal swing corresponding to firmware or software in the ASIC.
    • A logic unit for accessing the memory group through the first bus.
    • A second transmission bus between the logic unit and the ASIC, having a second programmable data rate and signal swing associated with firmware or software in the ASIC.

U.S. Patent No. 10,998,017 - “Dynamic random access memory applied to an embedded display port,” Issued May 4, 2021

The Invention Explained

  • Problem Addressed: The patent background discusses the panel self-refresh (PSR) feature in the embedded display port (eDP) standard, which saves power on portable devices by allowing the graphics processing unit (GPU) to turn off when the screen image is static. However, the timing controller's frame buffer, typically a dynamic random access memory (DRAM), continues to consume significant power, limiting the overall battery savings (’017 Patent, col. 1:21-61).
  • The Patented Solution: The invention claims a DRAM architecture specifically designed for low-power operation. It requires the DRAM's core memory cells and its associated peripheral circuits to operate at voltages "lower than 1.1V," a significant reduction from prior JEDEC standards. This lower operating voltage directly reduces the power consumption of the frame buffer, enhancing the effectiveness of PSR (’017 Patent, Abstract; col. 2:1-5).
  • Technical Importance: By enabling DRAM to operate at substantially lower voltages, the invention helps extend the battery life of portable electronics like laptops and smartphones that rely on panel self-refresh to conserve power (’017 Patent, col. 2:27-35).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶39).
  • The essential elements of claim 1 include:
    • A DRAM core cell supplied with a first voltage lower than 1.1V.
    • A peripheral circuit supplied with a second voltage lower than 1.1V.
    • The DRAM core cell and peripheral circuit are formed on a single chip, with the peripheral circuit being external to the DRAM core cell.
    • The first and second voltages are capable of making the DRAM be applied to an embedded display port (eDP).

U.S. Patent No. 11,894,098 - “Dynamic random access memory applied to an embedded display port,” Issued February 6, 2024

  • Technology Synopsis: This patent addresses the same technical problem as the ’017 Patent: high power consumption in DRAM frame buffers used in devices with eDP and panel self-refresh (’098 Patent, col. 1:21-61). The claimed solution is a DRAM architecture where both the core cell and peripheral circuit operate at voltages below 1.1V, and critically, the voltage supplied to the core cell is different from the voltage supplied to the peripheral circuit (’098 Patent, Claim 1).
  • Asserted Claims: Independent claim 1 (Compl. ¶53).
  • Accused Features: The LPDDR5 DRAM in Apple’s products, which allegedly uses different low-voltage rails (VDD2H and VDD2L) to power the core and peripheral circuits, respectively, during Dynamic Voltage and Frequency Scaling (DVFS) operation (Compl. ¶¶57-58).

U.S. Patent No. 12,154,652 - “Dynamic random access memory applied to an embedded display port,” Issued November 26, 2024

  • Technology Synopsis: Also related to the ’017 and ’098 patents, this invention targets power reduction in DRAM for eDP applications (’652 Patent, col. 1:21-61). The solution requires a DRAM where the core cell is supplied with a first voltage and an input/output (I/O) circuit is supplied with a third voltage, with both voltages being below 1.1V and the first voltage being different from the third voltage (’652 Patent, Claim 1).
  • Asserted Claims: Independent claim 1 (Compl. ¶66).
  • Accused Features: The LPDDR5 DRAM in the accused products, which allegedly uses separate and distinct low-voltage power rails for the DRAM core (e.g., VDD2H/VDD2L) and the I/O circuit (VDDQ) (Compl. ¶¶70-72).

U.S. Patent No. 9,164,942 - “High speed memory chip module and electronics system device with a high speed memory chip module,” Issued October 20, 2015

  • Technology Synopsis: This patent addresses inefficiencies in standardized memory modules by proposing a more integrated architecture (’942 Patent, col. 1:26-51). The invention describes a system where a "logic unit" accesses memory ICs over a first transmission bus and converts the data into a second set of parallel data, with a different bus width, for transmission to an ASIC processor over a second transmission bus. This conversion of bus width allows for architectural optimization between the memory and processor domains (’942 Patent, Claim 19).
  • Asserted Claims: Independent claim 19 (Compl. ¶80).
  • Accused Features: The integrated memory controller (IMC) within Apple's A16 SoC, which is alleged to interface with LPDDR5 DRAM over a wide bus (e.g., x64) and convert that data for transmission to the processor cores over a different-width internal bus architecture (e.g., AXI interconnect) (Compl. ¶¶85, 88-89).

III. The Accused Instrumentality

Product Identification

  • The complaint accuses Apple products that have included LPDDR5 DRAM since September 2019, including the iPhone 14 and later, certain MacBook models, and certain iPad models (Compl. ¶13). The iPhone 14 Pro, which contains the A16 Bionic System-on-Chip (SoC), is used as a representative example for the infringement allegations (Compl. ¶20).

Functionality and Market Context

  • The allegations center on the architecture of Apple's A16 Bionic SoC, which integrates high-performance processor cores with a package containing LPDDR5 DRAM (Compl. ¶¶20-21). The complaint identifies the integrated memory controller (IMC) as the component managing data traffic between the processor and the DRAM (Compl. ¶25). A key accused functionality is the use of Dynamic Voltage and Frequency Scaling (DVFS), a feature of the LPDDR5 standard that allows the system to programmatically adjust the memory's operating frequency and voltage to balance performance and power consumption (Compl. ¶24). The complaint alleges these products are commercially significant consumer electronics devices.

IV. Analysis of Infringement Allegations

’834 Patent Infringement Allegations

Claim Element (from Independent Claim 21) Alleged Infringing Functionality Complaint Citation Patent Citation
an application-specific integrated circuit (ASIC) processor The Apple A16 Bionic chip, which includes CPU and GPU cores. ¶21 col. 8:10-24
a type of memory cell array group...comprises multiple memory cell array ICs The LPDDR5 DRAM package integrated with the A16 chip, which is comprised of multiple memory ICs. ¶22 col. 4:40-45
a first transmission bus...having a first programmable transmitting or receiving data rate, a first programmable...signal swing The memory bus between the A16's IMC and the LPDDR5 DRAM, which supports LPDDR5 DVFS to adjust frequency (data rate) and voltage (signal swing). ¶¶23-24 col. 4:54-61
a logic unit...for accessing the type of memory cell array group The integrated memory controller (IMC) within the A16 Bionic processor. ¶25 col. 4:46-49
a second transmission bus...having a second programmable...data rate, a second programmable...signal swing The on-chip interconnect between the IMC and the processor cores, which allegedly operates under mechanisms like Collaborative Processor Performance Control (CPPC) to adjust core frequency and voltage. ¶¶27-29 col. 4:62-67

The complaint provides an annotated die shot of the A16 chip identifying an area for the IMC and the connections to processor cores and LPDDR5 memory, which it labels as "the first transmission bus" and "the second transmission bus" (Compl. p. 16).

  • Identified Points of Contention:
    • Scope Questions: A primary question may be whether the integrated memory controller (IMC) within the A16 SoC can be considered a "logic unit" that is structurally or conceptually separate from the "ASIC processor" as required by the claim structure. The defense may argue they are inseparable parts of a single processor.
    • Technical Questions: What evidence does the complaint provide that the on-chip interconnect between the IMC and the processor cores constitutes a "second transmission bus" with its own independently programmable signal swing and data rate, as opposed to these parameters being inherent properties of the processor cores themselves?

’017 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a DRAM core cell...is supplied with a first voltage...lower than 1.1V The LPDDR5 DRAM core cells, which are allegedly powered by the VDD2H or VDD2L voltage rails during DVFSC mode, which are typically below 1.1V. ¶¶41-42 col. 6:3-6
a peripheral circuit...is supplied with a second voltage...lower than 1.1V The peripheral circuits of the LPDDR5 DRAM, also allegedly powered by the VDD2H or VDD2L rails, which operate below 1.1V. ¶43 col. 6:7-10
the DRAM core cell and the peripheral circuit are formed on a single chip, and the peripheral circuit is external to the DRAM core cell The LPDDR5 DRAM is alleged to be manufactured on a single chip with peripheral circuits architecturally external to the memory cell arrays. ¶44 col. 6:11-12
wherein the first voltage and the second voltage are capable of making the DRAM be applied to an embedded display port (eDP) The accused Apple devices are alleged to utilize an eDP protocol to communicate with certain displays. ¶45 col. 6:13-15

The complaint includes a JEDEC standards table showing recommended operating conditions for LPDDR5, where the maximum voltage for the VDD2H rail is 1.12V and the typical is 1.05V (Compl. p. 20). The complaint also provides a diagram illustrating the distinct "DRAM Core" and "peripheral circuit" blocks within a DRAM architecture powered by different voltage rails (Compl. p. 21).

  • Identified Points of Contention:
    • Scope Questions: What is the required technical nexus for the voltages to be "capable of making the DRAM be applied to an eDP"? Does this require the low-voltage mode to be specifically enabled by or for eDP operation, or is the mere presence of both technologies in the same device sufficient?
    • Technical Questions: The infringement theory relies on typical values from the JEDEC LPDDR5 standard. What evidence shows that Apple's specific implementation in the accused products actually operates the core and peripheral circuits at voltages that are, in practice, "lower than 1.1V" during the accused modes of operation?

V. Key Claim Terms for Construction

’834 Patent: "logic unit"

  • Context and Importance: The infringement theory depends on mapping Apple's IMC to the "logic unit" element, which the claim positions between the memory array and the "ASIC processor." If the IMC is construed as being part of the "ASIC processor," the three-part claim structure may not be met.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification suggests the logic unit's function can be a "parallel-to-serial controller" (’834 Patent, col. 4:5-8), a generic function that an IMC performs. This may support viewing it as a functional block rather than a physically separate chip.
    • Evidence for a Narrower Interpretation: Patent figures depict the "Logic unit 106" as a distinct block separate from the "ASIC processor 112," which could support an interpretation requiring some level of physical or at least clear architectural separation, not just a functional region within a monolithic SoC (’834 Patent, Fig. 1).

’017 Patent: "peripheral circuit"

  • Context and Importance: The claim requires a structural distinction between the "DRAM core cell" and the "peripheral circuit," which must be "external to the DRAM core cell." The definition of this term will be critical for determining whether the accused LPDDR5 DRAM, with its various internal power domains, satisfies this limitation.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent does not provide a specific definition, which may suggest the term should be given its plain and ordinary meaning in the art, which would typically include circuitry like sense amplifiers, decoders, and data path logic that support the memory array.
    • Evidence for a Narrower Interpretation: The specification and figure consistently depict the "memory core unit 102" and "peripheral circuit unit 104" as two distinct, high-level functional blocks (’017 Patent, Fig. 1; col. 4:58-63). This could be argued to require a clear architectural boundary, not just any circuit that is not a memory cell.

VI. Other Allegations

  • Indirect Infringement: For all asserted patents, the complaint alleges induced infringement, stating that Apple’s affirmative acts of manufacturing, distributing, and providing user documentation instruct and encourage customers to use the accused products in an infringing manner (Compl. ¶¶33, 47, 60, 74, 91). The complaint also pleads contributory infringement, alleging the accused components are material to the inventions, are not staple articles of commerce, and have no substantial non-infringing uses (Compl. ¶¶34, 48, 61, 75, 92).
  • Willful Infringement: The complaint alleges that Apple had pre-suit knowledge of the patents, or was willfully blind, due to its position as a major technology company that monitors advances in memory technology (Compl. ¶14). It further alleges that the filing of the lawsuit provides Apple with actual knowledge for any ongoing infringement (Compl. ¶15).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core architectural question for the ’834 and ’942 patents will be one of structural mapping: can the highly integrated functional areas of Apple's SoC—such as the processor cores, on-chip interconnects, and integrated memory controller—be discretely mapped onto the patent's claimed elements of an "ASIC processor," a "logic unit," and distinct "transmission buses," or does the monolithic design of the accused chip create a fundamental mismatch?
  • A key evidentiary question for the ’017, ’098, and ’652 patents will be one of operational proof: can the plaintiff demonstrate that Apple's accused LPDDR5 DRAM actually operates its core, peripheral, and I/O circuits at voltages below the claimed 1.1V threshold and in the specific, distinct voltage configurations required by each patent, moving beyond the general specifications of the JEDEC standard to the proven functionality of the accused products themselves?