DCT
7:25-cv-00505
Chip Packaging Tech LLC v. STMicroelectronics Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Chip Packaging Technologies, LLC (Texas)
- Defendant: STMicroelectronics, Inc. (Delaware)
- Plaintiff’s Counsel: Blue Peak Law Group LLP
- Case Identification: 7:25-cv-00505, W.D. Tex., 10/30/2025
- Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant maintains established and regular places of business in the District, including an office in Austin, and has committed acts of infringement there. The complaint also notes that Defendant has previously admitted to having facilities and employees in the District in prior patent litigation.
- Core Dispute: Plaintiff alleges that Defendant’s semiconductor products, including certain MOSFETs, microcontrollers (MCUs), and pressure sensors, infringe five patents related to semiconductor packaging methods and structures.
- Technical Context: The patents-in-suit relate to fundamental aspects of semiconductor packaging, a field focused on protecting integrated circuits while providing electrical connections and managing thermal performance.
- Key Procedural History: The complaint does not mention any prior litigation involving the asserted patents or any administrative proceedings such as inter partes reviews. It does cite several other patent cases against the Defendant in the same district to support its venue allegations.
Case Timeline
| Date | Event |
|---|---|
| 2012-07-17 | ’189 Patent Priority Date |
| 2014-02-04 | U.S. Patent No. 8,643,189 Issues |
| 2014-07-02 | ’299 Patent Priority Date |
| 2014-07-18 | ’351 Patent Priority Date |
| 2015-08-23 | ’646 Patent Priority Date |
| 2016-02-16 | U.S. Patent No. 9,263,299 Issues |
| 2016-03-29 | U.S. Patent No. 9,299,646 Issues |
| 2016-04-11 | ’658 Patent Priority Date |
| 2017-06-20 | U.S. Patent No. 9,685,351 Issues |
| 2018-12-11 | U.S. Patent No. 10,151,658 Issues |
| 2025-10-30 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,263,299 - “Exposed Die Clip Bond Power Package”
Issued February 16, 2016
The Invention Explained
- Problem Addressed: The patent’s background section describes the need for semiconductor packaging that enhances thermal performance and reduces electrical resistance (known as Rpson), particularly for power devices like field-effect transistors (FETs) (’299 Patent, col. 1:47-57).
- The Patented Solution: The invention is a manufacturing method where multiple semiconductor dies are placed on a temporary carrier tape. A pre-formed lead frame is then attached directly to the bond pads on the top surface of the dies using solder paste. This "clip bond" process creates a direct, low-resistance connection. The underside of the die, which has a solderable coating, is left exposed in the final package to allow for efficient heat dissipation to a printed circuit board (’299 Patent, Abstract; col. 2:1-9).
- Technical Importance: This method aims to improve two critical metrics for power semiconductors: lowering electrical resistance for higher efficiency and providing a direct thermal path away from the die to prevent overheating (’299 Patent, col. 1:47-57).
Key Claims at a Glance
- The complaint asserts independent Claim 1 (Compl. ¶43).
- Essential elements of Claim 1 include:
- mounting a plurality of active device die, which have been back-ground and have a solderable underside, onto a temporary carrier;
- dispensing a solder paste onto the bond pads of the die;
- attaching a lead frame to the temporary carrier such that its upper portions contact the solder paste and its lower portions contact the temporary carrier; and
- reflowing the solder to create a connection between the upper lead frame portions and the bond pads.
U.S. Patent No. 9,299,646 - “Lead Frame With Power And Ground Bars”
Issued March 29, 2016
The Invention Explained
- Problem Addressed: In conventional semiconductor packages, bond wires carrying sensitive input/output (I/O) signals often pass over or near a "power bar" that supplies electricity to the die. This proximity can cause the power bar to induce electrical noise in the sensitive signal wires, corrupting the signals (’646 Patent, col. 1:10-20).
- The Patented Solution: The invention introduces an electrically grounded "ground bar" into the lead frame structure, positioned physically between the signal leads and the power bar. This ground bar acts as a shield, intercepting and diverting the electrical noise emanating from the power bar, thereby protecting the signal integrity of the I/O connections (’646 Patent, Abstract; col. 2:5-9).
- Technical Importance: By improving noise immunity, this design allows for more reliable signaling in densely packed semiconductor devices, which is critical for the performance of complex integrated circuits (’646 Patent, col. 1:21-24).
Key Claims at a Glance
- The complaint asserts independent Claim 1 (Compl. ¶64).
- Essential elements of Claim 1 include:
- a semiconductor die with first (signal) and second (power) contact pads;
- a package casing covering the die;
- a plurality of signal leads connected to the first contact pads;
- a power bar located between the signal leads and the die, connected to the second contact pad; and
- an electrically grounded ground bar with a first portion located between the signal leads and the power bar, and a second portion located between the power bar and the semiconductor die.
U.S. Patent No. 8,643,189 - “Packaged Semiconductor Die with Power Rail Pads”
Issued February 4, 2014
- Technology Synopsis: The patent addresses the challenge of distributing power and ground across a semiconductor die that has a high number of external connections. The solution involves adding large, non-circuit metal pads, called "power rail pads," directly onto the die's surface to serve as intermediate distribution hubs. These rails allow a few external power connections to be efficiently distributed to many internal power pads on the die via short wire bonds, reducing complexity and stray capacitance (’189 Patent, Abstract; col. 1:12-45).
- Asserted Claims: Claim 1 (Compl. ¶83).
- Accused Features: The STMicro Mainstream Arm Cortex-M0+ MCU family (e.g., STM32G071CB) is accused of incorporating a semiconductor die with these power rail pad structures (Compl. ¶81).
U.S. Patent No. 9,685,351 - “Wire Bond Mold Lock Method And Structure”
Issued June 20, 2017
- Technology Synopsis: The patent addresses delamination, a common failure mode where the plastic mold compound separates from the metal lead frame in a package. The invention describes a method of creating "positive mold lock structures"—such as dummy wire bond loops or stud bumps—that protrude from the lead frame surface. During encapsulation, the liquid mold compound flows around and under these structures, creating a strong mechanical interlock upon hardening that enhances adhesion and prevents delamination (’351 Patent, Abstract; col. 2:26-51).
- Asserted Claims: Claim 1 (Compl. ¶101).
- Accused Features: The STMicro SR5 E1 Series 32-bit MCUs are accused of being manufactured using a process that forms these positive mold lock structures on the lead frame (Compl. ¶99).
U.S. Patent No. 10,151,658 - “Pressure-sensing Integrated Circuit Device with Diaphragm”
Issued December 11, 2018
- Technology Synopsis: The patent relates to pressure sensors that use a flexible gel to transmit ambient pressure to a sensing element. It identifies a problem where the gel can be damaged by environmental contaminants. The proposed solution is to cover the flexible gel with a "flexible diaphragm," which acts as a protective barrier against harmful materials while still being pliable enough to accurately transmit pressure changes to the underlying gel and sensor (’658 Patent, Abstract; col. 2:3-6).
- Asserted Claims: Claim 1 (Compl. ¶118).
- Accused Features: The STMicro LPS28DFW product line is accused of being a pressure-sensing IC that includes a flexible gel covered by a protective flexible diaphragm (Compl. ¶116, ¶121-122).
III. The Accused Instrumentality
Product Identification
The complaint accuses multiple distinct product families, each corresponding to a different asserted patent. These include the POWERFLAT MOSFETs (STL220N6F7), the Chorus family of MCUs (SPC582B60E1), the Arm Cortex-M0+ MCUs (STM32G071CB), the SR5 E1 Series MCUs (SR5E1E7), and the LPS28DFW pressure sensors (Compl. ¶¶41, 62, 81, 99, 116).
Functionality and Market Context
The accused products are semiconductor components sold for a variety of applications, including automotive and general-purpose electronics (Compl. ¶¶33, 35). The complaint alleges that these products are available for purchase in the United States through Defendant’s website and authorized distributors (Compl. ¶¶33-38). An image from STMicro's website shows the STL220N6F7 POWERFLAT MOSFET is available for purchase (Compl. ¶34, p. 7).
IV. Analysis of Infringement Allegations
’299 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| mounting a plurality of active device die...onto a temporary carrier, each said active device die having bond pads, each of said active device die having a solderable conductive surface on its underside; and having been subjected to back-grinding to a prescribed thickness; | The accused products are allegedly made by mounting multiple active dies, which have bond pads, a solderable underside, and are back-ground to a specific thickness, onto a temporary carrier. | ¶45, ¶46 | col. 3:10-21 |
| dispensing a solder paste onto the bond pads on the plurality active device die; | Solder paste is allegedly dispensed onto the bond pads of the active dies. | ¶47 | col. 3:36-38 |
| attaching a lead frame to the temporary carrier...wherein upper lead frame portions contact the solder paste present on the bond pads and lower lead frame portions contact the temporary carrier; | A lead frame is allegedly attached so its upper parts contact the solder paste and its lower parts contact the temporary carrier. | ¶48, ¶49, ¶50 | col. 3:39-45 |
| reflowing the solder so that a connection is made between the upper lead frame portions and the bond pads of the plurality of active device die. | The solder is allegedly reflowed to form an electrical and mechanical connection between the lead frame and the die's bond pads. | ¶51 | col. 3:46-49 |
- Identified Points of Contention:
- Scope Questions: A potential issue may be the scope of the term "temporary carrier." While the patent specification provides an example of a specific thermal release tape, the claim language is not so limited, raising the question of what range of manufacturing substrates this term covers (’299 Patent, col. 3:12-18).
- Technical Questions: The complaint relies on microscopy images and an Energy-dispersive X-ray spectroscopy (EDS) map to allege the required process steps (Compl. ¶51). A key evidentiary question will be whether this reverse-engineering analysis can definitively prove that the specific, multi-step method claimed by the patent was actually used to manufacture the accused products.
’646 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a semiconductor die having a plurality of first contact pads and at least one second contact pad disposed on or exposed through a surface thereof; | The accused MCU allegedly includes a semiconductor die with distinct first contact pads (for signals) and second contact pads (for power). | ¶66 | col. 2:40-45 |
| a package casing that covers the semiconductor die; | The accused MCU allegedly includes a package casing that encapsulates the die. | ¶67 | col. 2:35-37 |
| a plurality of signal leads spaced apart from the semiconductor die and each having an embedded portion located within the package casing...each of the signal leads being electrically connected to a respective one of the first contact pads; | The product allegedly has multiple signal leads, partially embedded in the casing, that are electrically connected to the first contact pads on the die. | ¶68 | col. 2:48-54 |
| a power bar extending at least partially in an area between the embedded portions of the plurality of signal leads and the semiconductor die...the power bar being electrically connected to the at least one second contact pad; | A structure identified as a "power bar" is allegedly located between the signal leads and the die and is connected to the second contact pad. An annotated X-ray image illustrates this alleged structure (Compl. ¶69). | ¶69, ¶70 | col. 3:5-10 |
| a ground bar that is electrically grounded...the ground bar having a first portion disposed between the embedded portions of the plurality of signal leads and the first side of the power bar, and a second portion disposed between the second side of the power bar and the semiconductor die. | A structure identified as a "ground bar" is allegedly positioned to shield the signal leads from the power bar. An X-ray image with color-coded annotations depicts this alleged arrangement (Compl. ¶71). | ¶71 | col. 3:41-49 |
- Identified Points of Contention:
- Scope Questions: The central dispute may turn on the construction of "ground bar." The defense may argue the term requires a structure that provides a specific, measurable level of electrical shielding, while the plaintiff may argue it is defined purely by its physical location as described in the claim.
- Technical Questions: The complaint alleges the accused "ground bar" is "electrically grounded" but supports this with an X-ray image that shows physical structure, not electrical properties (Compl. ¶71). A key factual question will be whether the accused structure is, in fact, electrically grounded and functions as the claimed shield.
V. Key Claim Terms for Construction
Patent ’299: "temporary carrier"
- Context and Importance: This term is critical because the claim requires specific physical interactions with it: the die is mounted onto it, and the lower lead frame portions contact it. Its definition could influence whether the accused manufacturing process meets these limitations.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim language itself is broad, imposing no material or structural limits on the "temporary carrier." The specification's general description refers simply to a "temporary carrier," which could suggest any substrate used temporarily during assembly (’299 Patent, col. 2:1-3).
- Evidence for a Narrower Interpretation: The detailed description discloses a specific embodiment using "REVALPHA® tape," a "thermal release sheet material" (’299 Patent, col. 3:12-18). This specific example could be used to argue for a narrower construction limited to carrier tapes with similar properties.
Patent ’646: "ground bar"
- Context and Importance: This term is the central feature of the invention, intended to solve the problem of noise coupling. The entire infringement analysis for the ’646 patent hinges on whether the accused structure meets the definition of a "ground bar."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: Claim 1 defines the term structurally based on its location: "a first portion disposed between the...signal leads and the...power bar, and a second portion disposed between the...power bar and the semiconductor die" (’646 Patent, cl. 1). This language could support an interpretation where any grounded conductor in that specific location infringes, regardless of its shielding efficacy.
- Evidence for a Narrower Interpretation: The patent's background explicitly states the problem is "noise coupling" and the goal is to "improve[] noise immunity" (’646 Patent, col. 1:10-24). This stated purpose could support an argument that "ground bar" implicitly requires the structure to actually function as an effective noise shield, not just be coincidentally placed in the claimed location.
VI. Other Allegations
- Indirect Infringement: For all five patents, the complaint alleges induced infringement under 35 U.S.C. § 271(b). The allegations are based on Defendant having knowledge of the patents (at least upon filing of the complaint) and causing infringement by "contracting for the third-party manufacture of, and/or providing the Accused Products to direct infringers" such as foundries, customers, and end-users (e.g., Compl. ¶¶53-54, 73-74).
- Willful Infringement: The complaint alleges that Defendant had knowledge of the patents and infringement "at least as of the date of this Complaint" (e.g., Compl. ¶53). This frames the willfulness allegation as being based on potential post-suit conduct rather than pre-suit knowledge.
VII. Analyst’s Conclusion: Key Questions for the Case
- Evidentiary Proof for Method Claims: For the patents claiming manufacturing methods (’299 and ’351 Patents), a central challenge for the Plaintiff will be to gather evidence, likely from third-party manufacturers, to prove that every step of the claimed methods is practiced in the precise sequence required to produce the accused products.
- Functional vs. Structural Claim Scope: For the apparatus patents (’646, ’189, and ’658 Patents), the case may turn on claim construction. A core issue will be whether terms like "ground bar" and "power rail pad" are defined purely by their physical structure and location as recited in the claims, or if they must also be proven to perform the specific function described as the invention's purpose in the patent specification.
- Interpretation of Visual Evidence: The complaint's infringement theories rely heavily on annotated microscopy and X-ray images. A key factual dispute will likely involve contesting interpretations of this visual data, with each side presenting expert testimony on whether these images accurately and sufficiently depict the structures and arrangements required by the patent claims.