Chip Packaging Tech LLC v. STMicroelectronics Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Chip Packaging Technologies, LLC (Texas)
  • Defendant: STMicroelectronics, Inc. (Delaware)
  • Plaintiff’s Counsel: Blue Peak Law Group LLP
• Case Identification: 7:25-cv-00505, W.D. Tex., 01/22/2026
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant maintains an established place of business in the district, has transacted business there, and has committed acts of infringement within the district. The complaint also notes that Defendant has previously admitted to having facilities and employees in the district in prior litigation.
• Core Dispute: Plaintiff alleges that several of Defendant’s semiconductor product families infringe five patents related to different aspects of semiconductor packaging technology.
• Technical Context: The patents-in-suit concern methods and structures for packaging semiconductor dice, a critical manufacturing step that affects a device's thermal performance, electrical characteristics, and physical durability.
• Key Procedural History: This First Amended Complaint follows an original complaint that was allegedly served on the Defendant on November 4, 2025, a date Plaintiff uses to anchor its allegations of willful infringement.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,263,299 - "Exposed Die Clip Bond Power Package"

The Invention Explained

• Problem Addressed: The patent’s background section describes the challenge of creating semiconductor power packages with enhanced thermal performance and minimal electrical resistance (RDSon), which are critical for high-power applications (’299 Patent, col. 1:47-54).
• The Patented Solution: The invention is a method for packaging multiple device die by mounting them on a temporary carrier. A key feature is that the underside of each die has an exposed, solderable conductive surface. A lead frame is attached to bond pads on the top of the die using solder paste and a reflow process. This "clip bond" method, combined with the exposed die backside, is designed to improve thermal dissipation and lower electrical resistance (’299 Patent, Abstract; col. 2:6-10).
• Technical Importance: This manufacturing approach aims to improve the efficiency and reliability of power semiconductor devices by more effectively managing heat and electricity flow within the package (’299 Patent, col. 1:47-54).

Key Claims at a Glance

• The complaint asserts independent claim 1 (Compl. ¶43).
• Claim 1 recites a method for packaging an IC device with the following essential steps:
  • Mounting a plurality of active device die onto a temporary carrier, with each die having been back-ground and having a solderable underside.
  • Dispensing a solder paste onto bond pads on the die.
  • Attaching a lead frame to the temporary carrier, where upper lead frame portions contact the solder paste and lower lead frame portions contact the temporary carrier.
  • Reflowing the solder to create a connection between the upper lead frame portions and the bond pads.

U.S. Patent No. 9,299,646 - "Lead Frame With Power and Ground Bars"

The Invention Explained

• Problem Addressed: The patent’s background explains that in conventional semiconductor packages, bond wires carrying sensitive I/O signals often must pass over a "power bar," creating a risk of noise coupling and signal interference (’646 Patent, col. 1:13-20).
• The Patented Solution: The invention introduces an electrically grounded "ground bar" that is physically located between the signal leads and the power bar. As described in the specification, this ground bar acts as a shield to reduce or prevent noise from the power bar from interfering with the signals carried by the bond wires (’646 Patent, Abstract; col. 2:41-45). The ground bar is specifically claimed as having a portion between the signal leads and the power bar, and another portion between the power bar and the semiconductor die (’646 Patent, col. 6:20-25).
• Technical Importance: This structure improves signal integrity within a compact package, a critical factor for the reliable operation of complex integrated circuits (’646 Patent, col. 1:21-24).

Key Claims at a Glance

• The complaint asserts independent claim 1 (Compl. ¶64).
• Claim 1 recites a semiconductor device with the following essential elements:
  • A semiconductor die with first (signal) and second (power) contact pads.
  • A package casing.
  • A plurality of signal leads connected to the first contact pads.
  • A power bar located between the signal leads and the die, connected to the second contact pad.
  • A ground bar that is electrically grounded, having a first portion disposed between the signal leads and the power bar, and a second portion disposed between the power bar and the semiconductor die.

U.S. Patent No. 8,643,189 - "Packaged Semiconductor Die with Power Rail Pads"

• Patent Identification: U.S. Patent No. 8,643,189, "Packaged Semiconductor Die with Power Rail Pads", issued February 4, 2014 (Compl. ¶20).
• Technology Synopsis: The patent addresses inefficient power distribution within a semiconductor die by proposing the use of one or more large "power rail pads" on the die surface. These pads have a larger surface area than conventional connection pads and serve as a common distribution point, with die wire bonds connecting the power rail pad to multiple individual power or ground pads on the die. This design aims to reduce the number and length of wire bonds required to power the die (’189 Patent, Abstract; col. 1:26-44).
• Asserted Claims: Independent claim 1 (Compl. ¶83).
• Accused Features: The STMicro Mainstream Arm Cortex-M0+ MCU family (e.g., STM32G071CB), which allegedly contains "power rail pad structures" (Compl. ¶81).

U.S. Patent No. 9,685,351 - "Wire Bond Mold Lock Method and Structure"

• Patent Identification: U.S. Patent No. 9,685,351, "Wire Bond Mold Lock Method and Structure", issued June 20, 2017 (Compl. ¶22).
• Technology Synopsis: This patent addresses the problem of delamination, where the plastic molding compound separates from the underlying lead frame. The invention describes a method of forming "positive mold lock structures," such as dummy wire bond loops or stud bumps, on the surface of the lead frame. These structures protrude laterally and create a mechanical interlock with the molding compound as it cures, thereby improving adhesion and preventing separation (’351 Patent, Abstract; col. 1:30-45).
• Asserted Claims: Independent claim 1 (Compl. ¶101).
• Accused Features: The STMicro SR5 E1 Series 32-bit MCUs (e.g., SR5E1E7), which are alleged to be made using a process that creates "positive mold lock structures" (Compl. ¶99).

U.S. Patent No. 10,151,658 - "Pressure-sensing Integrated Circuit Device with Diaphragm"

• Patent Identification: U.S. Patent No. 10,151,658, "Pressure-sensing Integrated Circuit Device with Diaphragm", issued December 11, 2018 (Compl. ¶24).
• Technology Synopsis: The patent seeks to protect the flexible gel used in pressure sensors from environmental contaminants. The solution involves placing a "flexible diaphragm" over the gel, which in turn is covered by a lid containing an aperture. This construction allows ambient air pressure to be transmitted through the diaphragm to the pressure-sensing die while the diaphragm itself acts as a protective physical barrier against harmful materials (’658 Patent, Abstract; col. 1:3-6).
• Asserted Claims: Independent claim 1 (Compl. ¶118).
• Accused Features: The STMicro LPS28DFW product line, which is alleged to be a pressure sensor that includes a gel, diaphragm, and a holed lid (Compl. ¶¶116, 119).

III. The Accused Instrumentality

Product Identification

• The complaint accuses multiple product lines, each corresponding to one or more patents-in-suit: the MOSFET N-CH 60V 120A POWERFLAT product line (e.g., STL220N6F7); the 32-bit Power Architecture MCU Chorus family (e.g., SPC582B60E1); the Mainstream Arm Cortex-M0+ MCU family (e.g., STM32G071CB); the SR5 E1 Series 32-bit MCUs (e.g., SR5E1E7); and the LPS28DFW pressure sensor product line (Compl. ¶¶33, 41, 62, 81, 99, 116).

Functionality and Market Context

• The complaint alleges these products are semiconductor components, including power MOSFETs, microcontrollers for automotive and other applications, and water-resistant pressure sensors (Compl. ¶¶34-38, 119). Plaintiff asserts that these products are available for purchase in the United States through Defendant’s website and authorized distributors (Compl. ¶¶33, 38). The complaint includes a screenshot from Defendant's website showing authorized U.S. distributors (Compl. p. 6).

IV. Analysis of Infringement Allegations

U.S. Patent No. 9,263,299 Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: A central question may be the interpretation of "temporary carrier." Infringement of this method claim appears to depend on whether the accused manufacturing process utilizes a carrier that is later removed, as depicted in the patent's process flow (’299 Patent, FIG. 5, step 545), versus a permanent substrate.
  • Technical Questions: The complaint's allegations regarding Defendant's manufacturing process are made "on information and belief," acknowledging that the steps are not public (Compl. ¶48). A key question for discovery will be whether the annotated X-ray of the STL220N6F7 product accurately reflects a process meeting every step of the claimed method (Compl. p. 14).

U.S. Patent No. 9,299,646 Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: The infringement analysis may turn on the construction of the phrase "disposed between." Whether the structure identified as a "ground bar" in the 2-D X-ray (Compl. p. 27) satisfies the specific three-dimensional spatial requirements of having portions on both sides of the power bar could be a point of dispute.
  • Technical Questions: What evidence does the complaint provide that the structure identified as the "ground bar" is, in fact, "electrically grounded" as required by the claim? The complaint alleges this on "information and belief" but does not present direct evidence of the structure's electrical potential or function.

V. Key Claim Terms for Construction

U.S. Patent No. 9,263,299

• The Term: "temporary carrier"
• Context and Importance: The method claim requires mounting die onto a "temporary" carrier. The viability of the infringement claim depends on whether the substrate or tape used in the accused process is indeed temporary and later removed, as opposed to being a permanent part of the final package. Practitioners may focus on this term because it is a foundational step of the claimed method.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claims do not define the term, which may support giving it a plain and ordinary meaning not limited to a specific material. The specification describes an embodiment using a "carrier tape 120" on a "carrier ring apparatus 110," which could be argued as merely an example (’299 Patent, col. 4:6-9).
  • Evidence for a Narrower Interpretation: The specification's only detailed embodiment depicts a process flow that includes the explicit step "REMOVE CARRIER TAPE" (’299 Patent, FIG. 5, step 545). This could support an argument that the term is limited to a removable tape-based carrier as shown in the preferred embodiment.

U.S. Patent No. 9,299,646

• The Term: "a ground bar ... having a first portion disposed between ... the signal leads and the ... power bar, and a second portion disposed between the ... power bar and the semiconductor die"
• Context and Importance: This limitation defines the novel shielding structure of the invention. The infringement case hinges on whether the accused device contains a single, grounded structure with these specific and distinct positional relationships relative to the power bar.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the ground bar as providing "noise shielding" and being located "in the area 127 between the signal leads 122 and the semiconductor die 112" (’646 Patent, col. 3:41-45). This could support a functional definition where any grounded structure in that general area that provides shielding meets the limitation.
  • Evidence for a Narrower Interpretation: Figure 2 of the patent depicts the first and second portions (132a, 132b) in a clear, physically distinct arrangement on opposite sides of the power bar (124). A defendant may argue that the term requires this specific physical layout shown in the figures, rather than just a general location.

VI. Other Allegations

• Indirect Infringement: For each of the five asserted patents, the complaint alleges induced infringement under 35 U.S.C. § 271(b). The allegations are based on Defendant having knowledge of the patents since at least the date the original complaint was served (November 4, 2025) and acting with specific intent to cause infringement by third parties (e.g., foundries, distributors, end-users) by contracting for their manufacture and providing the accused products to them (Compl. ¶¶53-55, 73-75, 91-93, 107-109, 126-128).
• Willful Infringement: The complaint alleges that Defendant’s infringement was willful, based on its knowledge of the asserted patents as of the service date of the original complaint. The complaint states Defendant "was willfully blind to such infringement" (Compl. ¶53).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of process verification: for the asserted method claims ('299 and '351 patents), can Plaintiff's "information and belief" allegations about Defendant's proprietary manufacturing techniques be substantiated through discovery? Specifically, does the accused process for the POWERFLAT product line in fact utilize a "temporary carrier" as claimed in the '299 patent?
• A second central issue will be one of structural interpretation: for the asserted apparatus claims ('646, '189, and '658 patents), do the physical structures within the accused products, as depicted in Plaintiff’s annotated images, satisfy the specific spatial and functional requirements of the claims? For instance, regarding the '646 patent, is the metallic element identified in the X-ray of the Chorus MCU verifiably an "electrically grounded" bar with distinct portions situated "between" the power bar and other components as the claim language requires?