DCT

7:25-cv-00510

Adeia Semiconductor Bonding Tech Inc v. Advanced Micro Devices Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 7:25-cv-00510, W.D. Tex., 11/03/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant maintains a regular and established place of business in Austin, Texas, employs individuals in the district responsible for the accused product lines, and has previously admitted to proper venue in the district.
  • Core Dispute: Plaintiff alleges that Defendant’s advanced processors, which utilize 3D V-Cache™ hybrid bonding technology and are manufactured at advanced process nodes, infringe six patents related to semiconductor fabrication methods and device structures.
  • Technical Context: The lawsuit concerns foundational technologies in modern semiconductor manufacturing: hybrid bonding for 3D chip stacking and advanced patterning techniques for creating FinFET transistors at nanoscale dimensions.
  • Key Procedural History: The complaint notes that the asserted patents originate from the portfolios of Adeia’s predecessors, including Ziptronix, a pioneer in hybrid bonding, and from strategic acquisitions of technology developed by IBM, a leader in FinFET innovation.

Case Timeline

Date Event
2005-08-11 U.S. Patent No. 8,389,378 Priority Date
2013-03-05 U.S. Patent No. 8,389,378 Issued
2015-12-16 U.S. Patent No. 9,564,446 Priority Date
2016-05-19 U.S. Patent No. 10,879,226 Priority Date
2016-10-07 U.S. Patent No. 12,401,010 Priority Date
2016-10-17 U.S. Patent No. 10,283,592 Priority Date
2017-02-07 U.S. Patent No. 9,564,446 Issued
2017-12-14 U.S. Patent No. 11,978,639 Priority Date
2019-05-07 U.S. Patent No. 10,283,592 Issued
2020-12-29 U.S. Patent No. 10,879,226 Issued
2024-05-07 U.S. Patent No. 11,978,639 Issued
2025-08-26 U.S. Patent No. 12,401,010 Issued
2025-11-03 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,389,378 - "3D IC Method and Device" (Issued Mar. 5, 2013)

The Invention Explained

  • Problem Addressed: The patent's background describes the increasing difficulty and cost associated with fabricating vertical interconnections needed to stack integrated circuits (ICs) for improved density and performance (US 8,389,378 B2, col. 1:44-2:4).
  • The Patented Solution: The invention discloses a method of integrating two semiconductor elements by first forming a via in one element, filling it with a conductive material, and then bonding that element to a second element. A defining feature of the process is that the via and its conductive material are formed before the final "first contact structure" is created on the surface, after which a portion of the first element is removed to expose the conductive material within the via for bonding (US 8,389,378 B2, col. 4:62-65; Abstract).
  • Technical Importance: This method provides a "via-first" or "via-middle" approach to creating high-density, direct connections between stacked chips, a foundational concept for modern 3D IC packaging technologies like hybrid bonding (Compl. ¶7).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶80).
  • Essential elements of Claim 1 (a method) include:
    • forming a via in a first element;
    • forming a first conductive material in the via;
    • connecting the conductive material to a first contact structure;
    • removing a portion of the first element to expose the conductive material in the via;
    • bonding the first element to a second element to directly connect either the first contact structure or the first conductive material to a second contact structure; and
    • performing the via and conductive material formation steps before forming the first contact structure.
  • The complaint reserves the right to assert additional claims (Compl. ¶79).

U.S. Patent No. 10,879,226 - "Stacked Dies and Methods For Forming Bonded Structures" (Issued Dec. 29, 2020)

The Invention Explained

  • Problem Addressed: The patent background identifies challenges in stacking thinned semiconductor dies, which are fragile and susceptible to stress-induced damage during thinning and subsequent handling processes (US 10,879,226 B2, col. 1:21-34).
  • The Patented Solution: The invention proposes a method where singulated dies are first bonded to a carrier, then thinned. A "protective material" is subsequently applied over the exposed surfaces of the thinned dies, including their sidewalls. After this protective step, a second die is directly bonded on top of the first die, with the protective material serving to mitigate damage and stress (US 10,879,226 B2, col. 2:25-30; Abstract). The method is illustrated in the patent's process flow diagrams (e.g., US 10,879,226 B2, Figs. 7A-7B).
  • Technical Importance: This methodology offers a framework for handling and stacking ultra-thin dies, enhancing manufacturing yield by protecting fragile structures throughout the complex 3D integration process (Compl. ¶¶7-8).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶112).
  • Essential elements of Claim 1 (a method) include:
    • directly bonding a plurality of singulated integrated device dies to a carrier;
    • after bonding, thinning the plurality of dies;
    • providing a protective material on exposed surfaces of the dies, including their sidewall surfaces; and
    • after providing the protective material, directly bonding a second singulated die to a first die from the plurality.
  • The complaint reserves the right to assert additional claims (Compl. ¶111).

U.S. Patent No. 12,401,010 - "3D Processor Having Stacked Integrated Circuit Die"

  • Issued: August 26, 2025
  • Technology Synopsis: The patent describes a 3D processor where one IC die containing a processor core is vertically stacked with another IC die containing a cache. The invention specifies that the cache vertically overlaps the processor core and that the two are communicatively coupled through a hybrid bond comprising directly bonded metal contact pads and non-conductive regions (US 12,401,010 B2, Abstract).
  • Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶141).
  • Accused Features: Plaintiff alleges that AMD’s MI300A product, which vertically stacks a cache die on a processor core die using hybrid bonding, infringes the ’010 patent (Compl. ¶¶142, 144, 146, 150).

U.S. Patent No. 9,564,446 - "SRAM Design to Facilitate Single Fin Cut in Double Sidewall Image Transfer Process"

  • Issued: February 7, 2017
  • Technology Synopsis: The patent addresses challenges in fabricating FinFETs using double-patterning techniques. It discloses a method to create fin pairs with two distinct spacings by manipulating mandrel shapes, which makes it easier to subsequently remove unwanted "dummy" fins without damaging adjacent active fins, a process particularly relevant for dense SRAM designs (US 9,564,446 B1, Abstract).
  • Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶172).
  • Accused Features: The complaint accuses the manufacturing processes for AMD processors at 7nm and 6nm nodes, such as the Ryzen™ 5 3600X, alleging these products are made with a self-aligned quadruple patterning (SAQP) process that results in the claimed fin structures with dual spacings (Compl. ¶¶173, 176, 190).

U.S. Patent No. 11,978,639 - "Two-Color Self-Aligned Double Patterning (SADP) To Yield Static Random Access Memory (SRAM) and Dense Logic"

  • Issued: May 7, 2024
  • Technology Synopsis: The patent details a "two-color" self-aligned double patterning (SADP) manufacturing process. This method uses two different lithography masks to create mandrel patterns that are intentionally unequally spaced. This approach is designed to create complex fin layouts with variable pitches while avoiding the creation of unwanted "dummy" fins that would otherwise require a separate removal step (US 11,978,639 B2, Abstract).
  • Asserted Claims: The complaint asserts independent claim 9 (Compl. ¶211).
  • Accused Features: Plaintiff accuses AMD’s processors made with 5nm and/or 4nm processes, exemplified by the AMD Ryzen™ 7600X. The complaint alleges that analysis of the product reveals a fin pattern with different pitches indicative of the claimed two-color SADP method (Compl. ¶¶212, 224).

U.S. Patent No. 10,283,592 - "Approach to Minimization of Strain Loss in Strained Fin Field Effect Transistors"

  • Issued: May 7, 2019
  • Technology Synopsis: This patent describes a vertical FinFET device structure aimed at preserving mechanical strain in the transistor's fin, which is critical for enhancing performance. The claimed structure includes specific elements, notably an "insulating liner" that is in contact with the endwall of the fin segments and extends from within the substrate up to the top of an adjacent gate spacer, designed to prevent strain loss (’592 Patent, Abstract; Claim 1).
  • Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶243).
  • Accused Features: The complaint accuses AMD products made with a 3nm process, exemplified by the AMD EPYC™ 9645. It alleges these products contain vertical fin devices with strained segments and insulating liners that match the claimed structure (Compl. ¶¶244, 246, 254).

III. The Accused Instrumentality

Product Identification

The complaint identifies two main categories of accused products: "Accused HB Products," which are processors employing hybrid bonding (e.g., AMD's 3D V-Cache™ technology), and "Accused APN Products," which are processors manufactured using advanced process nodes (e.g., 7nm down to 3nm) that include FinFETs (Compl. ¶¶35-39). Specific product families named include EPYC™, Ryzen™, Instinct™, and Radeon™ (Compl. ¶¶38-39).

Functionality and Market Context

The relevant functionality of the Accused HB Products is the use of hybrid bonding to stack an L3 cache die directly on top of a processor core die, enabling higher performance through increased cache size and lower latency (Compl. ¶35). A marketing image from AMD describes this as "HYDROPHILIC DIELECTRIC-DIELECTRIC BONDING + DIRECT CU-CU BONDING" (Compl. ¶81). The relevant functionality of the Accused APN Products is the use of advanced lithography techniques, such as multi-patterning, to manufacture FinFET transistors at cutting-edge nodes, which is essential for transistor density and efficiency improvements (Compl. ¶¶39, 176). The complaint alleges these technologies are central to AMD's high-performance product offerings (Compl. ¶7).

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,389,378 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A method of integrating a first element... with a second element... AMD's EPYC™ 9684X integrates a first element (e.g., cache die) with a second element (e.g., processor die) via hybrid bonding. ¶81 col. 3:10-12
forming a via in said first element. The accused product is constructed by forming a via in the first element. ¶83 col. 3:13-14
forming a first conductive material in said via. The complaint does not provide sufficient detail for analysis of this specific element, though it is implied by subsequent steps. - col. 3:14-15
connecting said first conductive material to said first contact structure. The accused product is constructed by connecting the conductive material in the via to a copper contact structure. ¶85 col. 3:15-17
removing a portion of said first element to expose said first conductive material in said via. The accused product is constructed by removing a portion of the first element to expose conductive material (copper) in the via. ¶87 col. 4:1-3
bonding said first element to said second element such that one of said first contact structure and said first conductive material is directly connected to said second contact structure. The accused product is constructed by bonding the first element to the second, directly connecting a copper contact structure of the first element to one on the second. The complaint provides a diagram from AMD showing direct Cu-Cu bonding (Compl. p. 22). ¶89 col. 4:4-9
wherein said via and said first conductive material are formed before forming said first contact structure. The accused product is constructed by forming the via and filling it with conductive material before forming the corresponding copper contact structure on the filled via. ¶91 col. 4:62-65

Identified Points of Contention

  • Scope Questions: The infringement analysis may focus on the term "contact structure." A central question will be whether AMD's process involves an intermediate conductive layer that is later processed into the final contact structure, and if so, whether that initial layer qualifies as the "first contact structure" under the patent's definition. The claim's temporal requirement—that the via is formed before the contact structure—makes this definition critical.
  • Technical Questions: A factual question for the court may be to determine the precise sequence of AMD's manufacturing process. The complaint's theory relies on an interpretation of AMD's public diagrams, and discovery will likely be needed to confirm whether the alleged sequence of forming, filling, and then creating a contact structure accurately reflects AMD's proprietary fabrication flow.

U.S. Patent No. 10,879,226 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A method for packaging integrated device dies, the method comprising: The AMD MI300A is constructed by packaging integrated device dies, as illustrated in a diagram showing the "Modular Chiplet Package" (Compl. p. 29). ¶113 col. 1:15-18
directly bonding a plurality of singulated integrated device dies to a carrier... comprising a first singulated device die. The AMD MI300A is constructed by directly bonding multiple singulated dies (e.g., CPU Complex Dies and Accelerator Complex Dies) to a carrier (e.g., a silicon interposer). ¶115 col. 4:5-10
after directly bonding, thinning the plurality of singulated integrated device dies. The accused product is constructed by thinning the integrated device dies after they have been directly bonded. ¶117 col. 3:9-12
providing a protective material on exposed surfaces of the plurality singulated integrated device dies including sidewall surfaces... The accused product is constructed by providing a protective material on exposed surfaces, including sidewalls, of the singulated dies. ¶119 col. 2:25-30
and after providing the protective material, directly bonding a second singulated integrated device die to the first singulated device die. The accused product is constructed by directly bonding a second die to a first die after the protective material has been provided. ¶121 col. 2:50-54

Identified Points of Contention

  • Scope Questions: The case may turn on the construction of "carrier" and "protective material." A question for the court will be whether the "silicon interposer" in AMD's MI300A architecture (Compl. p. 29) functions as the "carrier" recited in the claim, or if it is itself considered one of the "integrated device dies." Furthermore, the analysis will question whether any material used by AMD in its packaging process performs the function of a "protective material" as taught by the patent, specifically in protecting die sidewalls during thinning.
  • Technical Questions: Evidentiary questions may arise regarding the function and timing of application for any materials used by AMD between its stacked dies. It will need to be determined if such materials are applied for protection during thinning, as required by the claim's sequence, or if they are applied later in the process primarily for structural support or thermal management.

V. Key Claim Terms for Construction

For U.S. Patent No. 8,389,378

  • The Term: "contact structure"
  • Context and Importance: The definition is critical because Claim 1 requires the via and its conductive fill to be formed before the "first contact structure." How this term is defined will determine the point in the manufacturing timeline against which AMD's process is compared. Practitioners may focus on this term because if an early-stage conductive layer in AMD's process is deemed the "contact structure," the claim's temporal limitation may not be met.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent frequently uses the term without a specific structural definition, referring to it as an element for electrical connection (US 8,389,378 B2, col. 3:15-17), which may support a broad interpretation covering various types of conductive pads or layers.
    • Evidence for a Narrower Interpretation: The patent's figures depict the "contact structure" (e.g., 17 in Fig. 1) as a distinct, final feature on the surface of the device region, suggesting it is the terminal connection point, not an intermediate layer ('378 Patent, Fig. 1).

For U.S. Patent No. 10,879,226

  • The Term: "protective material"
  • Context and Importance: Infringement of Claim 1 requires "providing a protective material on exposed surfaces... including sidewall surfaces" after thinning the dies. The case may depend on whether any material AMD uses, such as an underfill or molding compound, qualifies as this claimed element.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the material's function as being to "protect the die during thinning" and reduce stress, and notes it "may comprise one or more protective layers" ('226 Patent, col. 2:25-30). This functional language could support interpreting the term to include any material that provides such protection, regardless of its primary purpose.
    • Evidence for a Narrower Interpretation: The Abstract and detailed descriptions outline a specific sequence: mount, thin, provide protective layer, then bond another die on top. Figure 1C shows a distinct "first layer 12" applied over and around the thinned dies, suggesting a discrete material applied for this specific protective purpose, which could support a narrower construction ('226 Patent, Fig. 1C; col. 8:15-24).

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement by third parties, including wafer foundries (e.g., TSMC), assembly partners (ATMP), and customers. The allegations state that AMD's "agreements, directives, advertising, sales, design, development, and/or technical materials" instruct these third parties to make, use, sell, or import the accused products that are manufactured by the patented processes (Compl. ¶¶98-99, 128-129).
  • Willful Infringement: For all asserted patents, the complaint alleges willful infringement based on AMD's knowledge of the patents "since at least the filing of this Complaint" (Compl. ¶¶96, 101, 126, 131). This frames the willfulness claim based on post-suit conduct.

VII. Analyst’s Conclusion: Key Questions for the Case

The dispute appears to center on two primary axes of contention that will likely define the litigation:

  • A core issue will be one of process interpretation: Do AMD's proprietary manufacturing flows for its 3D V-Cache™ and advanced node products align with the specific sequences, structures, and material functions recited in Adeia's patents? This will involve a granular comparison of AMD's actual steps against claim limitations concerning the timing of "contact structure" formation (’378 patent), the application of "protective material" (’226 patent), and the multi-masking fin patterning methods (’446 and ’639 patents).
  • A key evidentiary question will be one of structural correlation: Can Plaintiff demonstrate, through reverse engineering and expert analysis of AMD's final products, that the observed microscopic structures—such as fin pitches in an SRAM cell or the composition of layers between stacked dies—are the necessary result of the specific manufacturing methods claimed in the patents-in-suit?