DCT
7:25-cv-00526
Polaris Innovations Ltd v. Qualcomm Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Polaris Innovations Limited (Ireland)
- Defendant: Qualcomm Incorporated and Qualcomm Technologies, Inc. (both Delaware)
- Plaintiff’s Counsel: Nelson Bumgardner Conroy PC
- Case Identification: 7:25-cv-00526, W.D. Tex., 11/14/2025
- Venue Allegations: Plaintiff alleges venue is proper because Defendant maintains at least two regular and established places of business in Austin, Texas, which is within the district.
- Core Dispute: Plaintiff alleges that Defendant’s processors and related platforms, which support industry-standard memory technologies, infringe three patents related to power reduction in memory devices and command protocols for integrated circuits.
- Technical Context: The patents relate to methods for improving power efficiency and data reliability in high-speed memory systems, a critical technology in mobile devices, automotive systems, and other electronics where performance and battery life are paramount.
- Key Procedural History: The complaint alleges that Plaintiff sent a pre-suit notice letter to Defendant identifying the asserted patents and accused products. For U.S. Patent No. 8,117,526, an inter partes review (IPR2019-01527) concluded with a certificate issued on February 15, 2023. The IPR resulted in the cancellation of several claims, but Claim 10, which is asserted in this complaint, was confirmed as patentable.
Case Timeline
| Date | Event |
|---|---|
| 2007-10-29 | ’526 Patent Priority Date |
| 2007-11-29 | ’526 Patent Application Filed |
| 2007-12-13 | ’798 Patent Application Filed |
| 2008-06-24 | ’264 Patent Application Filed |
| 2010-05-11 | ’264 Patent Issued |
| 2010-11-30 | ’798 Patent Issued |
| 2012-02-14 | ’526 Patent Issued |
| 2019-08-28 | IPR Proceeding Filed for ’526 Patent |
| 2023-02-15 | IPR Certificate Issued for ’526 Patent |
| 2025-11-14 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,715,264 - "Method and apparatus for selectively disabling termination circuitry," Issued May 11, 2010
The Invention Explained
- Problem Addressed: The patent's background describes how termination circuitry, necessary to prevent signal reflections during high-frequency operations (like memory reads/writes), unnecessarily consumes power during low-frequency operations (like self-refresh modes) when I/O signals are held at a static voltage different from the termination voltage (’264 Patent, col. 1:5-21, 1:45-54).
- The Patented Solution: The invention proposes control circuitry that selectively disables this termination circuitry during low-frequency states, such as a memory refresh operation, and re-enables it just before high-frequency operations resume. This method is designed to reduce static current draw and save power without compromising signal integrity during active use (’264 Patent, col. 2:59-col. 3:4; Fig. 2).
- Technical Importance: This technique provides a way to reduce standby power consumption in memory devices, a critical consideration for improving battery life in portable electronics and reducing energy costs in large-scale computing environments (’264 Patent, col. 3:2-4).
Key Claims at a Glance
- Independent Claim 1 is asserted (Compl. ¶30).
- A method of reducing power consumption by a memory device, comprising:
- disabling termination circuitry coupled to one or more input/output (I/O) signals of the memory device during at least a portion of a refresh operation performed by the memory device; and
- re-enabling the termination circuitry prior to the memory device resuming normal operation after completion of the refresh operation.
- The complaint expressly reserves the right to assert additional claims (Compl. ¶30, n.5).
U.S. Patent No. 7,844,798 - "Command protocol for integrated circuits," Issued November 30, 2010
The Invention Explained
- Problem Addressed: In conventional command protocols for integrated circuits, the circuitry responsible for receiving command "attributes" (e.g., memory addresses) must remain constantly powered on because it does not know in advance whether an incoming command will include such attributes. This leads to unnecessary power consumption, even when the device is in an active state (’798 Patent, col. 1:44-54).
- The Patented Solution: The invention proposes a two-part command protocol where the "instruction" portion is sent first, followed by the "attributes" portion after a defined delay. This delay gives the integrated circuit time to decode the instruction and, if attributes are expected, enable the corresponding receiver circuitry just in time to receive them. If no attributes are required, the receiver circuitry remains off, saving power (’798 Patent, Abstract; col. 2:30-44).
- Technical Importance: This protocol enables dynamic, fine-grained power management within an integrated circuit's active operational state, reducing energy use without the performance penalties associated with entering and exiting dedicated sleep modes (’798 Patent, col. 2:59-63).
Key Claims at a Glance
- Independent Claim 1 is asserted (Compl. ¶46).
- A method of operating an integrated circuit, the method comprising:
- supplying an instruction portion of an external command from an external controller to the integrated circuit to specify an operation to be performed by the integrated circuit; and
- for at least some types of instructions, supplying an attributes portion of the external command from the external controller to the integrated circuit to provide additional information about the operation to be performed, the attributes portion being supplied with a delay relative to the instruction portion, the delay providing sufficient time for the integrated circuit to enable receiver circuitry for processing the attributes portion in response to receipt of the instruction portion.
Multi-Patent Capsule: U.S. Patent No. 8,117,526 - "Apparatus and method for generating a transmit signal and apparatus and method for extracting an original message from a received signal," Issued February 14, 2012
- Technology Synopsis: This patent relates to combining Data Bus Inversion (DBI), a power-saving technique, with Error Correction Codes (ECC) for improved data reliability. The invention describes a method where the DBI indicator bit (which signals whether data is inverted) is itself protected by the ECC, allowing the system to perform error correction and bus inversion decoding in parallel while maintaining signal integrity (’526 Patent, Abstract; col. 2:40-47).
- Asserted Claims: Independent Claim 10 is asserted (Compl. ¶61).
- Accused Features: Plaintiff alleges that Defendant's products supporting LPDDR5/5X memory implement the JEDEC standard for Link ECC, which generates ECC check information based on both the data bits (DQ) and an inversion indicator (DMI). The complaint includes a JEDEC standard diagram illustrating the data flow for a memory write operation, showing an "ECC Generation" block that takes both "DQ" (data) and "DMI" (indicator) inputs, which Plaintiff alleges infringes the patent (Compl. ¶¶63-66; p. 27).
III. The Accused Instrumentality
- Product Identification: The Accused Instrumentalities include Qualcomm processors such as the Snapdragon 4, 6, 7, 8, and X Series; Qualcomm's Automotive platforms (e.g., Snapdragon Cockpit and Ride); and other platforms that support LPDDR5, LPDDR5X, and DDR4 memory standards (Compl. ¶¶10, 28, 44, 59). The Snapdragon 8 Gen 2 Mobile Platform is identified as a specific example (Compl. ¶32, 48).
- Functionality and Market Context: The complaint alleges these processors function as memory controllers that implement industry-standard (JEDEC) protocols for communicating with memory devices. The relevant functionalities include placing memory into low-power states (such as "Deep Sleep Mode") and issuing command sequences (such as PRECHARGE) that involve specific signal timing. The complaint asserts that these standard-compliant operations map directly onto the steps of the asserted patent claims (Compl. ¶¶32, 49). These processors are central components in a vast range of consumer and enterprise electronics, including smartphones and automotive infotainment systems.
IV. Analysis of Infringement Allegations
7,715,264 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| disabling termination circuitry coupled to one or more input/output (I/O) signals of the memory device during at least a portion of a refresh operation performed by the memory device | Accused Products issue commands to LPDDR5/5X memory to enter "Deep Sleep Mode," which the complaint characterizes as a self-refresh operation. During this mode, the memory's on-die termination (CS_ODT) circuitry is turned off. A JEDEC standard diagram is provided to show the state transition into Deep Sleep Mode (Compl. p. 12). | ¶34 | col. 4:56-62 |
| and re-enabling the termination circuitry prior to the memory device resuming normal operation after completion of the refresh operation. | Accused Products issue commands that cause the LPDDR5/5X memory to turn its CS_ODT circuitry back on prior to exiting Deep Sleep Mode and resuming normal operation. A JEDEC timing diagram is provided to illustrate this sequence (Compl. p. 13). | ¶35 | col. 5:1-12 |
- Identified Points of Contention:
- Scope Questions: A central question may be whether the "Deep Sleep Mode" in the LPDDR5/5X standard, a modern low-power state, qualifies as a "refresh operation" as that term is used in the context of the ’264 Patent, which was filed in 2008 and describes "self-refresh" in DRAM.
- Technical Questions: Does the accused processor (the memory controller) perform the claimed method, or does it merely issue standard JEDEC commands that cause the separate memory device to perform the method? The claim is for a "method of reducing power consumption by a memory device," raising the question of which entity is the direct infringer.
7,844,798 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| supplying an instruction portion of an external command from an external controller to the integrated circuit to specify an operation to be performed by the integrated circuit | The Accused Products, acting as external memory controllers, supply an instruction portion of a command (e.g., PRECHARGE) to the memory on command lines at the rising edge (R1) of the clock, as shown in a JEDEC "Command Truth Table" (Compl. p. 19). | ¶49 | col. 6:27-33 |
| for at least some types of instructions, supplying an attributes portion of the external command... with a delay relative to the instruction portion | For the PRECHARGE command, the Accused Products supply the attributes portion (bank addresses) to the memory on the falling edge (F1) of the clock, which is delayed relative to the instruction portion supplied on the rising edge. | ¶50 | col. 6:34-40 |
| the delay providing sufficient time for the integrated circuit to enable receiver circuitry for processing the attributes portion in response to receipt of the instruction portion | The complaint alleges that the one-clock-cycle delay between the rising and falling clock edges "allows for sufficient time to process the attributes portion of the command in response to receipt of the instruction portion." | ¶50 | col. 6:40-44 |
- Identified Points of Contention:
- Scope Questions: Does the standard timing separation between rising and falling edges of a clock in a DDR memory interface constitute the patented "delay"? The defense may argue the patent contemplates an additional, non-standard delay introduced specifically for power management, not incidental timing inherent to the DDR protocol.
- Technical Questions: The complaint alleges the delay provides "sufficient time" to enable circuitry but does not explicitly state that the accused products' receivers are, in fact, being powered down and then re-enabled during this interval. The key factual question will be whether the accused products actually use this delay for the claimed power-saving purpose or if it is merely a feature of the JEDEC standard with a different technical motivation.
V. Key Claim Terms for Construction
For the ’264 Patent:
- The Term: "refresh operation"
- Context and Importance: Plaintiff's infringement theory relies on construing this term to encompass the "Deep Sleep Mode" of modern LPDDR5/5X memory. The viability of the infringement case for the ’264 Patent may depend on whether this mode is considered a type of "refresh operation."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification characterizes the relevant state more generally as a "low frequency operation which does not cause substantial signal reflections" (’264 Patent, col. 1:50-54) and later gives a "memory refresh operation" as one example (’264 Patent, col. 2:54-55). This may support a construction covering various low-power, data-retention states.
- Evidence for a Narrower Interpretation: The patent’s detailed description focuses specifically on "self-refresh" operations as understood in the context of GDDRx and DDRx SDRAM at the time of invention (’264 Patent, col. 4:48-53). This could support an argument that the term is limited to those specific, conventional refresh modes.
For the ’798 Patent:
- The Term: "delay providing sufficient time for the integrated circuit to enable receiver circuitry"
- Context and Importance: This term contains the functional essence of the invention. Infringement requires not just a temporal delay between command parts, but a delay that serves the specific purpose of allowing circuitry to be powered on. Practitioners may focus on whether the inherent timing of the JEDEC protocol meets this functional requirement.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification notes that the delay can be "roughly 1-4 nanoseconds," which is consistent with a modern high-speed clock cycle, and states the purpose is to allow "necessary parts of the receiver circuitries" to be activated (’798 Patent, col. 7:24-30). This could support Plaintiff's view that the half-cycle delay in the JEDEC standard is sufficient and meets the claimed function.
- Evidence for a Narrower Interpretation: The patent repeatedly frames the invention as introducing an "extra" or "additional" delay compared to conventional protocols where instruction and attributes are sent together (’798 Patent, Fig. 1; Fig. 4). This may support a narrower construction requiring a delay added specifically for power-gating purposes, rather than one that is an inherent part of standard DDR signal timing.
VI. Other Allegations
- Indirect Infringement: For all three patents, the complaint alleges inducement of infringement. It asserts that Defendant knowingly encourages infringement by providing customers with datasheets, technical documentation, and support materials that instruct them to operate the accused processors in a manner that practices the claimed methods (Compl. ¶¶36-37, 51-52, 72-73).
- Willful Infringement: The complaint alleges willful infringement for all asserted patents, based on Defendant’s alleged knowledge of the patents from a pre-suit notice letter sent by Plaintiff. The complaint alleges that Defendant continued its infringing conduct despite this knowledge (Compl. ¶¶22, 38, 53, 74).
VII. Analyst’s Conclusion: Key Questions for the Case
This case appears to center on the common patent litigation strategy of mapping patented concepts onto functionalities required by widely adopted industry standards. The resolution will likely depend on the court's interpretation of claim scope and the factual evidence presented regarding the operation of the accused devices. The key open questions include:
- A core issue will be one of definitional scope: Can terms from patents filed over a decade ago, such as "refresh operation" and a command "delay," be construed to cover modern, technically distinct implementations like "Deep Sleep Mode" and standard DDR clock edge timing as defined in the JEDEC standard?
- A second issue will be one of functional proof: For the ’798 patent, can Plaintiff provide evidence that the accused devices actually use the fractional-clock-cycle delay between command and attribute signals for the claimed purpose of enabling and disabling receiver circuitry, or is this timing merely an incidental feature of the JEDEC standard with no connection to the patented power-saving method?
- A third question relates to direct infringement liability: For the method claims asserted, who is the direct infringer? Is it the Defendant, whose memory controllers issue commands, or is it the separate memory devices from third parties that execute those commands? This may shift the focus of the case from direct infringement to the more demanding standards of proving inducement.