DCT
7:25-cv-00533
Vampire Labs LLC v. Advanced Micro Devices Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Vampire Labs, LLC (Texas)
- Defendant: Advanced Micro Devices, Inc. (Delaware)
- Plaintiff’s Counsel: Reichman Jorgensen Lehman & Feldberg LLP; DiNovo Price LLP
- Case Identification: 7:25-cv-00533, W.D. Tex., 11/14/2025
- Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant AMD maintains regular and established places of business, including a large Austin campus, and has committed the alleged acts of infringement within the district.
- Core Dispute: Plaintiff alleges that Defendant’s microprocessors, including its CPU and GPU product lines, infringe three patents related to fine-grained power gating technologies designed to reduce static power dissipation.
- Technical Context: The technology addresses the problem of static, or "leakage," power consumption in modern semiconductors, which becomes a dominant source of energy loss as transistor dimensions shrink.
- Key Procedural History: The complaint alleges that AMD was made aware of U.S. Patent No. 9,098,271, one of the patents-in-suit, as early as August 24, 2017, when it was cited by the U.S. Patent and Trademark Office during the prosecution of one of AMD's own patent applications. This allegation forms a basis for the claim of willful infringement.
Case Timeline
| Date | Event |
|---|---|
| 2012-02-02 | Earliest Priority Date for ’048 Patent |
| 2012-02-05 | Earliest Priority Date for ’271 and ’416 Patents |
| 2015-08-04 | ’271 Patent Issued |
| 2015-08-11 | ’416 Patent Issued |
| 2015-12-22 | ’048 Patent Issued |
| 2016-01-01 | Alleged Launch of GCN 4.0 (Baffin) Architecture |
| 2017-08-24 | ’271 Patent allegedly cited against AMD in USPTO Office Action |
| 2025-11-14 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,218,048 - "Individually activating or deactivating functional units in a processor system based on decoded instruction to achieve power saving"
The Invention Explained
- Problem Addressed: The patent’s background section describes the growing problem of static power dissipation, or "leakage power," in modern microprocessors. As transistors shrink, this leakage becomes the dominant form of power loss, and functional units (FUs) that are idle but still powered contribute significantly to this waste, reducing battery life and increasing heat (’048 Patent, col. 1:11-37).
- The Patented Solution: The invention proposes a fine-grained power gating system where the processor’s instruction decoder determines which specific FU is needed for an incoming instruction. A power controller then activates only that necessary FU for the minimum number of clock cycles required to execute the operation, deactivating it immediately afterward to prevent both static and dynamic power loss. This is a reactive, instruction-driven approach that avoids predictive logic (’048 Patent, Abstract; col. 2:10-21).
- Technical Importance: This method provides a more precise and efficient way to manage power compared to "coarse-grained" techniques that power gate entire processor cores or rely on prediction-based algorithms, which can be inaccurate and introduce latency (Compl. ¶¶35-36).
Key Claims at a Glance
- The complaint asserts at least independent claim 1 (Compl. ¶46).
- Claim 1, a system claim, requires:
- An instruction decoder configured to decode an instruction.
- A power controller unit coupled to the instruction decoder.
- A first functional unit coupled to the power controller and decoder.
- A plurality of switches coupling the power controller and functional unit, configurable to improve power-up latency by accelerating in-rush current.
- The power controller is configured to determine whether the functional unit is needed based on data from the instruction decoder.
- The power controller is configured to activate/deactivate the functional unit, powering it on for the minimal number of clock cycles needed.
- The functional unit is prevented from incurring static and dynamic power loss when deactivated.
- The complaint asserts infringement under the doctrine of equivalents if literal infringement is not found (Compl. ¶47).
U.S. Patent No. 9,104,476 - "Autonomous microprocessor re-configurability via power gating pipelined execution units using dynamic profiling"
The Invention Explained
- Problem Addressed: Like the ’048 Patent, this invention targets power waste from idle FUs. The focus here is on developing a power-gating strategy that can adapt to the changing, real-time workload of the processor rather than relying on a fixed, pre-determined profile (’416 Patent, col. 1:29-45).
- The Patented Solution: The invention describes a method of dynamic profiling. A performance monitoring unit collects performance data on FU utilization during operation. This data is used to determine a utilization level, which is compared against a threshold. If a condition is met (e.g., utilization falls below the threshold), the FU is power gated. The system uses lookup tables to store profiles for different software processes, allowing these power-saving settings to be reloaded quickly during an operating system context switch (’416 Patent, Abstract; col. 2:10-37).
- Technical Importance: This dynamic approach allows power management to be tailored to the actual, real-time demands of running applications, potentially offering more effective power savings than a purely static, one-size-fits-all analysis.
Key Claims at a Glance
- The complaint asserts at least independent claim 1 (Compl. ¶62).
- Claim 1, a method claim, requires:
- Using a performance monitoring unit to collect performance data for a functional unit.
- Determining a utilization level of the functional unit based on the performance data.
- Comparing the utilization level with a threshold.
- Power gating the functional unit when a condition is satisfied.
- Updating a configuration register that controls a power switch for the functional unit.
- Updating a lookup table with information to limit startup time during a context switch.
- Storing specific needs values for multiple processes in the lookup table to permit their reuse during context switches.
- The complaint asserts infringement under the doctrine of equivalents if literal infringement is not found (Compl. ¶63).
U.S. Patent No. 9,098,271 - "Autonomous microprocessor re-configurability via power gating pipelined execution units using static profiling"
Technology Synopsis
This patent discloses a method for power gating FUs based on a static analysis of software code. A static code profiler, operating during the compilation process on a developer processor, determines which FUs a program will require. This information is stored in a "specific needs profile" that is later used by the target processor at runtime to power gate any unneeded units, thereby saving power without the overhead of real-time hardware monitoring (’271 Patent, Abstract; col. 2:44-53).
Asserted Claims
At least Claim 1 (Compl. ¶81).
Accused Features
The complaint alleges that AMD's developer tools, such as the ROCProfiler and Radeon GPU Profiler, function as the claimed static code profilers. These tools allegedly analyze software to determine functional unit needs for target processors, such as those with the RDNA architecture (Compl. ¶¶83-84).
III. The Accused Instrumentality
Product Identification
The complaint broadly accuses AMD's modern CPU and GPU product lines. Specific examples include CPUs with "Zen 3+ and later" architectures (such as the Ryzen 6000 series) and GPUs with "Baffin and later" architectures (such as the RDNA architecture) (Compl. ¶¶44, 48, 64).
Functionality and Market Context
The accused products are alleged to implement "fine-grained power gating" to manage power consumption (Compl. ¶44). This functionality is allegedly controlled at a "per cu" (per compute unit) or "per-thread" level, managed by technologies AMD markets as "PowerPlay" and controlled by a System Management Unit (SMU) (Compl. ¶¶42, 52). The complaint includes a marketing graphic for the Zen 3+ architecture, Fig. 048-3, which touts "deeper control over every individual processing thread's power level and clock" as a feature for securing "more performance per watt" (Compl. p. 13). This technology is central to the performance and efficiency of AMD's processors, which compete in markets from mobile devices to data centers.
IV. Analysis of Infringement Allegations
’048 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| [a] an instruction decoder of a processor... configured to decode an instruction | Accused Products are processors that inherently include one or more instruction decoders to translate machine code into control signals (Compl. ¶51, Fig. 048-2). | ¶51 | col. 2:15-16 |
| [b] a power controller unit coupled to the instruction decoder | The Accused Products contain a System Management Unit (SMU) that acts as a power controller and is coupled to the processor's core components (Compl. ¶52). | ¶52 | col. 4:8-10 |
| [c] a first functional unit of the processor coupled to the power controller unit and the instruction decoder | The Zen 3+ architecture includes functional units such as Integer and Floating Point Units that are coupled to the SMU (Compl. ¶54, Fig. 048-6). | ¶54 | col. 3:6-10 |
| [d] a plurality of switches... configurable to improve the power up latency... via accelerating in-rush current | The Zen 3+ architecture allegedly uses switches for power gating and includes "hardware-assisted accelerators for faster switching of components' sleep and wake-up states" to reduce latency (Compl. ¶55, Fig. 048-9). | ¶55 | col. 2:37-41 |
| [e] wherein the power controller unit is configured to determine whether the first functional unit should be used... based on data of the instruction decoder | In the Zen 3+ architecture, the SMU allegedly "activates and deactivates functional units of the processor core based on decoded instructions within execution threads" (Compl. ¶56). | ¶56 | col. 1:53-57 |
| [f] ...performing at least one of activating and deactivating the functional unit... for the minimal number of clock cycles needed to execute the instruction | The complaint alleges AMD's "Per-Thread Power/Clock Control" allows energy to be allocated only to parts of a core that need to be operated (Compl. ¶56, Fig. 048-11). | ¶56 | col. 1:57-61 |
| [g] wherein the first functional unit is prevented from incurring static power loss and dynamic power loss when deactivated | When functional units are power gated, power is turned off, which prevents them from incurring static power loss (Compl. ¶57). | ¶57 | col. 2:41-43 |
Identified Points of Contention
- Scope Questions: A central question may be whether AMD's System Management Unit (SMU), which the complaint alleges communicates "per-thread" utilization to the operating system (Compl. ¶53), operates "based on data of the instruction decoder" as required by claim 1[e]. The analysis may focus on whether the SMU's decisions are directly driven by the output of the decoder for a given instruction, or by higher-level, OS-mediated information about thread status.
- Technical Questions: Claim 1[d] requires switches that improve power-up latency by "accelerating in-rush current." The complaint cites AMD documents describing "hardware assisted acceleration for very fast transitions" (Compl. p. 15, Fig. 048-7), but it may become a point of dispute whether this mechanism works by accelerating in-rush current as specified in the claim.
’416 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| [a] using a performance monitoring unit... collecting performance data of a first type of functional unit in an execution stage of the processor's pipeline | On information and belief, AMD's RDNA processors have a performance monitoring unit. The complaint points to the ROCProfiler tool as demonstrating the capability to collect performance data from functional units (Compl. ¶65, Fig. 416-1). | ¶65 | col. 2:10-15 |
| [b] determining a utilization level of the first type of functional unit based on the performance data | The complaint alleges that performance counters in the RDNA architecture are used to "quantify the performance of the underlying architecture showcasing which pieces of the computational pipeline... are being utilized" (Compl. ¶68, Fig. 416-3). | ¶68 | col. 2:15-17 |
| [c] comparing the utilization level... with a first threshold | The complaint asserts that using performance counters for optimization "necessarily entails comparing the extracted performance counters to a threshhold of some type" (Compl. ¶70). | ¶70 | col. 2:17-19 |
| [d] when a first condition has been satisfied, power gating at least one of the first type of functional unit | The RDNA architecture is alleged to enable fine-grained power gating, which involves toggling power on and off when defined conditions are met (Compl. ¶72, Fig. 416-5). | ¶72 | col. 2:19-21 |
| [e] updating a configuration register that controls a switch governing power | In the power gating process, the RDNA Architecture is alleged to update a configuration register that controls a power switch (Compl. ¶73). | ¶73 | col. 2:22-24 |
| [f] updating a lookup-table... wherein the configuration register is updated using information from the lookup-table during the context switch | The RDNA architecture allegedly updates a lookup table used for dynamic profiling, and the register is updated from this table during a context switch (Compl. ¶74). | ¶74 | col. 2:25-31 |
| [g] wherein the lookup-table stores specific needs values for a plurality of processes... to permit reuse | The RDNA architecture is alleged to employ a lookup table that stores specific values for different processes to permit reuse during context switches (Compl. ¶75). | ¶75 | col. 2:32-37 |
Identified Points of Contention
- Scope Questions: The complaint relies heavily on documentation for AMD's developer profiling tools (e.g., ROCProfiler) to support its infringement allegations for the dynamic profiling claims (Compl. ¶¶65, 70). A key question for the court will be whether the accused products perform this claimed method during normal end-user operation, or if these functionalities are merely diagnostic tools available to developers.
- Technical Questions: What evidence does the complaint provide that the accused products actually "compare" a utilization level to a "threshold" during operation, as required by claim 1[c]? The complaint asserts this "necessarily entails" such a comparison but provides limited direct evidence of this specific step occurring in the accused products themselves (Compl. ¶70).
V. Key Claim Terms for Construction
For the ’048 Patent
- The Term: "based on data of the instruction decoder" (Claim 1)
- Context and Importance: This term is critical for defining the trigger for the power gating decision. Its construction will determine whether infringement requires a direct, one-to-one link between a decoded instruction and a power controller's action, or if it can cover more complex, system-level decisions (like AMD's alleged "per-thread" control) that are indirectly informed by the instruction stream.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent's block diagram in Figure 4 simply shows the "Power Controller Unit" coupled to the "ID" (Instruction Decode) stage, without specifying the nature of the data exchanged, which may support a broader reading (’048 Patent, Fig. 4).
- Evidence for a Narrower Interpretation: The patent's flowchart in Figure 7 depicts a series of direct logical checks based on instruction type (e.g., "Does instruction Require Integer Unit"), which may suggest that the "data" is the specific identity of the instruction type itself, supporting a narrower interpretation (’048 Patent, Fig. 7).
For the ’416 Patent
- The Term: "collecting performance data of a first type of functional unit in an execution stage of the processor's pipeline" (Claim 1)
- Context and Importance: This term defines where and what kind of data must be collected. Practitioners may focus on this term because its construction will determine if high-level metrics (e.g., overall CPU load) suffice, or if the claim requires granular data sourced directly from hardware counters associated with specific functional units within the processor's pipeline. The complaint references both high-level profile types (Fig. 416-1) and low-level hardware counters (Fig. 416-3).
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent's background discusses the general goal of adapting to a program's needs, which could be accomplished with various types of performance data. The term "performance data" itself is not explicitly limited in the claims.
- Evidence for a Narrower Interpretation: The explicit limitation to data from an "execution stage of the processor's pipeline" could be argued to exclude data collected by higher-level software or drivers that are not integral to the pipeline itself, thereby requiring direct hardware-level monitoring.
VI. Other Allegations
Indirect Infringement
The complaint alleges both induced and contributory infringement for all three patents. The allegations are based on claims that AMD provides its products with "technical manuals, source code, controllers, switches, firmware and compilers" and specifically intends for its customers to use the accused fine-grained power gating functionality (Compl. ¶¶58-59, 77-78, 89-90).
Willful Infringement
Willfulness is alleged based on AMD having received actual notice of the infringement at least upon the filing of the complaint (Compl. ¶92). More significantly, the complaint alleges pre-suit knowledge based on a Notice of References Cited issued by the USPTO against an AMD patent application on August 24, 2017, which included the ’271 Patent. The complaint argues this provided "formal legal notice" to AMD of the patent family and that continued infringement thereafter was knowing and reckless (Compl. ¶¶93-94, 96).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of evidentiary proof: does the functionality described in AMD’s developer tools and research papers, which the complaint heavily relies upon, accurately reflect the actual, real-time operation of its commercial processors in the hands of end-users, or are these features primarily for diagnostic or development purposes?
- A key question of claim construction will be the scope of "based on data of the instruction decoder" in the ’048 Patent. The dispute may center on whether this requires a direct, low-level signal from the decoder to the power controller, or if it can be read more broadly to cover system-level, per-thread power management that is ultimately driven by the nature of the underlying instructions being executed.
- A critical question for damages will be one of willfulness: did AMD's receipt of a USPTO Office Action citing the ’271 patent in 2017 constitute knowledge of the patent family sufficient to trigger a duty to investigate, and can its subsequent conduct be proven to be objectively reckless, potentially exposing it to enhanced damages?