DCT
7:25-cv-00551
Topwire LLC v. Apple Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: TopWire LLC (Texas)
- Defendant: Apple, Inc. (California)
- Plaintiff’s Counsel: THE MCCARTY FIRM, P.C.
- Case Identification: 7:25-cv-00551, W.D. Tex., 12/01/2025
- Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas based on Defendant’s maintenance of multiple regular and established places of business in the district, including corporate campuses, an engineering center, and several retail stores.
- Core Dispute: Plaintiff alleges that Defendant’s iPhone X and subsequent iPhone models, which feature a double-layered logic board, infringe a patent related to a "spacer connector" for stacking and electrically connecting semiconductor substrates.
- Technical Context: The technology at issue addresses advanced semiconductor packaging, a field focused on increasing the density of electronic components within compact devices by creating three-dimensional circuit structures.
- Key Procedural History: The complaint alleges Plaintiff sent a notice letter to Defendant on July 10, 2025, asserting infringement of the patent-in-suit. Defendant allegedly responded on July 22, 2025, but continued its accused activities, which forms the basis for the willfulness allegations. The patent was assigned to Plaintiff from the inventor on April 27, 2025.
Case Timeline
| Date | Event |
|---|---|
| 2015-06-24 | ’202 Patent Priority Date (via Provisional Application) |
| 2017-11-03 | Accused Product Launch (iPhone X) |
| 2018-01-02 | ’202 Patent Issue Date |
| 2025-04-27 | ’202 Patent assigned to Plaintiff TopWire LLC |
| 2025-07-10 | Plaintiff sends pre-suit notice letter to Defendant |
| 2025-07-22 | Defendant responds to Plaintiff's notice letter |
| 2025-12-01 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,859,202 - "Spacer Connector"
- Patent Identification: U.S. Patent No. 9,859,202, "Spacer Connector," issued January 2, 2018 (’202 Patent).
The Invention Explained
- Problem Addressed: The patent's background describes challenges in traditional semiconductor fabrication where stripping a "seed layer" after plating can reduce the size of circuits, which is a critical issue at the nanotechnology scale (’202 Patent, col. 1:13-25). More broadly, the invention addresses the need to increase component density in miniaturized electronics (Compl. ¶20).
- The Patented Solution: The invention is a structure and fabrication process for a "spacer connector" designed to be placed between two stacked substrates, such as circuit boards or chip packages. This connector simultaneously creates a physical space between the substrates and provides electrical pathways through "metal pillars" that pass through a "core substrate." This configuration allows for components, referred to as a "bottom chip," to be mounted in the newly created space, effectively enabling a 3D circuit layout (’202 Patent, Abstract; col. 2:31-41; Fig. 8).
- Technical Importance: This technology facilitates the vertical stacking of logic boards, which allows for a significant increase in the number of integrated circuits and other components without expanding the device's horizontal footprint (Compl. ¶¶ 18, 24).
Key Claims at a Glance
- The complaint asserts independent Claim 1 and reserves the right to assert additional claims (Compl. ¶35, n.10).
- Essential Elements of Claim 1:
- A structure comprising a bottom package substrate and a top package substrate stacked on top of it.
- At least one "spacer connector" interposed between the substrates, defining a space.
- The spacer connector itself comprises a core substrate, metal pillars passing through it, and top metal pads on the pillars.
- A specific structural feature where the bottom end of each metal pillar "protrudes downwardly" from the core substrate's bottom surface.
- Electrical coupling between the top and bottom substrates through the spacer connector's pillars and corresponding pillars on the substrates.
- A "bottom chip" arranged in the space and mounted to the top surface of the bottom package substrate.
- The structure includes two spacer connectors arranged on opposite sides of the bottom chip.
III. The Accused Instrumentality
Product Identification
The iPhone X and all subsequent iPhone models, with the iPhone 11 used as a representative example (Compl. ¶¶ 26, 36).
Functionality and Market Context
The complaint alleges that beginning with the iPhone X, Apple adopted a "double-layered logic board" design, also described as a "sandwiched" logic board (Compl. ¶¶ 24, 26). This design involves two separate printed circuit boards stacked vertically and connected. This approach allegedly allowed Apple to increase the density of components, supporting more features and functions without increasing the logic board's surface area (Compl. ¶24). The complaint provides a teardown image of an iPhone 11 to show its internal components before focusing on the logic board structure (Compl. ¶37). The complaint asserts this design provides Apple with "meaningful advantages over its smartphone competitors" (Compl. ¶32).
IV. Analysis of Infringement Allegations
’202 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a bottom package substrate; | The lower of the two printed circuit boards that form the iPhone's "sandwiched" logic board. The complaint presents a microscope cross-section identifying this component (Compl. ¶42). | ¶42 | col. 3:32-33 |
| a top package substrate stacked on top of the bottom package substrate; | The upper of the two printed circuit boards in the logic board assembly. The complaint shows this layer stacked on the bottom substrate in a cross-section image (Compl. ¶43). | ¶43 | col. 3:34-36 |
| at least one spacer connector interposed between the bottom package substrate and the top package substrate to define a space... | The vertical interconnect structures that join the top and bottom boards, creating a gap between them. The complaint provides a cross-section image labeling both the "Spacer Connector" and the "Space Between" (Compl. ¶44). | ¶44 | col. 3:37-41 |
| wherein the spacer connector comprises a core substrate; a plurality of metal pillars...and a plurality of top metal pads... | The interconnect structure is alleged to contain a core substrate with copper pillars passing through it, capped by metal pads. The complaint provides a magnified, labeled diagram of the alleged spacer connector's internal components (Compl. ¶45). | ¶45 | col. 3:42-48 |
| wherein a bottom end of each metal pillar...protrudes downwardly from a bottom surface of the core substrate, | The complaint alleges the metal pillars have bottom ends that protrude from the core substrate. This is identified in a labeled diagram derived from a microscope image (Compl. ¶45). | ¶45 | col. 3:49-51 |
| a bottom chip arranged in the space between the bottom package substrate and the top package substrate, wherein the bottom chip is mounted to the top surface of the bottom package substrate... | A chip is allegedly located in the space created by the spacer connectors and is mounted on the bottom board. A cross-section image in the complaint labels the "Bottom Chip," the "Space Between," and shows its position relative to the substrates (Compl. ¶49-50). | ¶¶49, 50 | col. 4:1-4 |
| the at least one spacer connector comprises two spacer connectors arranged on opposite sides of the bottom chip. | The logic board allegedly includes two such connector structures on either side of the bottom chip, defining a cavity. This arrangement is depicted in a cross-section image with the two "Spacer Connectors" highlighted (Compl. ¶51). | ¶51 | col. 4:5-8 |
Identified Points of Contention
- Scope Questions: The case may turn on whether the terms "package substrate" and "spacer connector," as defined in the patent, can be construed to read on the multi-layer printed circuit board assembly used in the iPhone. A potential dispute is whether a fully populated logic board constitutes a "package substrate" within the meaning of the patent, or if that term implies a more fundamental component used in initial chip packaging.
- Technical Questions: A central technical question will be whether the accused iPhone logic board meets the specific structural limitation that the "bottom end of each metal pillar... protrudes downwardly from a bottom surface of the core substrate." The infringement allegation relies on interpretation of microscope images, and the actual manufacturing process of the accused structure compared to the process described in the patent (’202 Patent, col. 2:50-53) may be a key point of dispute.
V. Key Claim Terms for Construction
The Term: "spacer connector"
- Context and Importance: This term defines the core of the claimed invention. The outcome of the case will heavily depend on whether the interconnect structure joining the two iPhone logic boards falls within the legal definition of this term.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim itself provides a structural definition: a "core substrate" with "metal pillars" and "top metal pads" (’202 Patent, cl. 1). Plaintiff may argue that any structure meeting these physical descriptions is a "spacer connector," regardless of its manufacturing method.
- Evidence for a Narrower Interpretation: The specification describes a specific fabrication process for the spacer connector that begins with a "temporary conductive carrier" and avoids the use of a "seed layer" that must later be stripped (’202 Patent, col. 1:13-25, col. 2:57-62). Defendant may argue that the term "spacer connector" is implicitly limited to a structure produced by this or a similar process, as this was the problem the inventor claimed to solve.
The Term: "package substrate"
- Context and Importance: Claim 1 requires a "top package substrate" and a "bottom package substrate." Whether the two populated printed circuit boards of the iPhone logic board meet this definition is critical to the infringement analysis.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent does not provide an explicit definition, so its plain and ordinary meaning could be argued to encompass any substrate that serves to package and interconnect electronic components, such as a logic board. The patent's figures depict "Substrate 1" and "Substrate 2" with chips mounted on them, which is analogous to the accused structure (e.g., ’202 Patent, Fig. 8).
- Evidence for a Narrower Interpretation: The term is used in the context of semiconductor packaging. Defendant may argue that in this field, a "package substrate" refers to a specific component used to interface a silicon die with a larger circuit board (e.g., a ball grid array substrate) and not the final, complex logic board itself.
VI. Other Allegations
- Indirect Infringement: The complaint alleges inducement of infringement, stating that Defendant encourages and instructs third parties (including customers and retailers) to use the accused iPhones through advertising, datasheets, instruction manuals, and other support materials (Compl. ¶54).
- Willful Infringement: Willfulness is alleged based on Defendant’s purported pre-suit knowledge of the ’202 Patent via a notice letter sent on July 10, 2025. The complaint alleges Defendant's continued infringement after receiving notice and failing to develop non-infringement theories constitutes "egregious behavior beyond typical infringement" (Compl. ¶¶ 30, 57, 19).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: Will the term "spacer connector", described in the patent specification in the context of a specific fabrication method aimed at solving a seed-layer-stripping problem, be construed broadly enough to encompass the board-to-board interconnect structure found in the accused iPhone logic boards, which may be manufactured via different processes?
- A key evidentiary question will be one of structural correspondence: Does the physical construction of the accused logic board meet the patent's specific claim requirements, particularly the limitation that the "bottom end of each metal pillar" must "protrude downwardly from a bottom surface of the core substrate"? This question will likely be decided through competing expert analyses of high-magnification microscopy images.