DCT

7:26-cv-00011

Fermat Intl Inc v. Advanced Micro Devices Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 7:26-cv-00011, W.D. Tex., 01/13/2026
  • Venue Allegations: Plaintiff alleges venue is proper based on Defendant maintaining regular and established places of business within the district, including multiple offices in Austin, and employing over 3,700 people in the district. The complaint also notes a prior patent infringement case involving the same accused product series where Defendant did not contest venue in this district.
  • Core Dispute: Plaintiff alleges that Defendant’s Instinct™ series of high-performance computing accelerators infringes three patents related to distributed hardware architectures for processing large datasets.
  • Technical Context: The technology at issue involves specialized hardware architectures for high-performance computing (HPC) and artificial intelligence (AI), a market critical for data centers and scientific research.
  • Key Procedural History: The complaint references Advanced Cluster Systems, Inc. v. Advanced Micro Devices, Inc., a prior case in the same district where Defendant's AMD Instinct™ MI200 Series Accelerators were accused of infringement and Defendant did not contest venue.

Case Timeline

Date Event
2019-02-06 Earliest Priority Date for ’512, ’750, and ’636 Patents
2023-01-10 U.S. Patent No. 11,550,512 Issues
2024-01-30 U.S. Patent No. 11,886,750 Issues
2025-04-08 U.S. Patent No. 12,271,636 Issues
2026-01-13 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 11,550,512 - *Analytics, algorithm architecture, and data processing system and method*, issued January 10, 2023

The Invention Explained

  • Problem Addressed: The patent's background describes a technical challenge where the rate of new data generation outpaces the processing capabilities of traditional hardware and software systems, making it increasingly difficult to solve large, complex data problems efficiently (’512 Patent, col. 1:46-54). Conventional systems are described as relying on "brute force" approaches that are costly in terms of cycle time and power consumption (’512 Patent, col. 1:55-61).
  • The Patented Solution: The invention proposes a distributed hardware architecture featuring one or more "compute nodes" designed to manage and execute data processing operations independently of a host computer (’512 Patent, col. 2:27-34). As depicted in Figure 1, this architecture uses a router module to connect a host system to a tiered series of compute nodes, creating a system intended to facilitate high-throughput data processing for resource-intensive applications (’512 Patent, Abstract; Fig. 1).
  • Technical Importance: The described solution aims to enhance efficiency and performance in processing massive datasets by creating a specialized, scalable hardware pipeline, moving away from conventional, computationally expensive methods (Compl. ¶24).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶30).
  • Claim 1 of the ’512 Patent recites the following essential elements for a data processing system:
    • A router module with a host interface and a node interface, communicatively coupled to a host compute system.
    • A plurality of serially coupled compute nodes arranged in an execution pipeline.
    • Each compute node comprises:
      • a communications link coupling the compute node to the router module's node interface, either directly or via an adjacent compute node;
      • a data store for records associated with a data processing operation;
      • a programmable logic component to execute the operation;
      • a node memory with data and instructions for the programmable logic and for inter-node communication;
      • a data mover component for intra-node communication between the programmable logic and node memory;
      • a storage interface component for intra-node communication between the programmable logic and the data store, which utilizes a plurality of communications channels.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 11,886,750 - *Analytics, algorithm architecture, and data processing system and method*, issued January 30, 2024

The Invention Explained

  • Problem Addressed: Like the related ’512 Patent, this patent addresses the problem of data volume growth outpacing the processing capabilities of traditional computing systems (’750 Patent, col. 1:51-58).
  • The Patented Solution: The patent describes a distributed hardware architecture, but the claims define a different topology than the ’512 Patent. The invention is summarized as a system for managing and executing data processing operations independently of a host, potentially distributed across various compute nodes (’750 Patent, Abstract). The architecture in claim 1 specifies a parallel-serial arrangement, with multiple compute nodes operating in parallel at a "first tier," which are then coupled to additional compute nodes in series (’750 Patent, col. 54:53-56).
  • Technical Importance: This architecture provides a specific, non-conventional technical solution for enhancing the efficiency and performance of processing large datasets (Compl. ¶26).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶54).
  • Claim 1 of the ’750 Patent recites the following essential elements for a data processing system:
    • A router module with a host interface and a node interface, communicatively coupled to a host compute system.
    • Multiple parallel first tier compute nodes coupled to one or more additional compute nodes in series.
    • Each compute node comprises: a communications link, a data store, a programmable logic component, a node memory, a data mover component, and a storage interface component that utilizes a plurality of communications channels.
  • The complaint does not explicitly reserve the right to assert dependent claims.

Multi-Patent Capsule

  • Patent Identification: U.S. Patent No. 12,271,636 - Analytics, algorithm architecture, and data processing system and method, issued April 8, 2025.
  • Technology Synopsis: This patent, part of the same family, also addresses specific, non-conventional technical advancements for processing large datasets (Compl. ¶28). The invention claimed is a "compute node" itself, rather than a full system. A key feature of the claimed compute node is a "node memory further compris[ing] algorithm memory including resource-specific memory locations...to support the data processing operation" (’636 Patent, col. 55:20-23).
  • Asserted Claims: The complaint asserts at least independent claim 1 (Compl. ¶73).
  • Accused Features: The complaint alleges that the AMD Instinct™ MI200 Series Accelerator is the claimed "compute node" (Compl. ¶74). Specific accused features include the accelerator's communications link (Infinity Fabric), data store (HBM2e memory), programmable logic component (Compute Units), and node memory (L2 Cache) (Compl. ¶¶75-78). The allegation of "resource-specific memory locations" is supported by reference to AMD's documentation on "atomic operations" executed in the L2 cache (Compl. ¶79).

III. The Accused Instrumentality

Product Identification

The complaint identifies AMD's Instinct™ Accelerators, including the MI200 and MI300 series, as the "Accused Products" (Compl. ¶7).

Functionality and Market Context

The Accused Products are described as data processing systems designed for high-performance computing (HPC) and AI applications at data center scale (Compl. ¶7). The complaint focuses on the MI200 Series Accelerator, alleging it is a multi-die Graphics Processing Unit (GPU) based on AMD’s CDNA™ architecture (Compl. ¶¶8, 35). This architecture is alleged to comprise two Graphics Compute Dies (GCDs), which function as compute nodes, serially coupled via an "In-package Infinity Fabric" (Compl. ¶35). These accelerators operate in cooperation with a host CPU, such as AMD's EPYC, via an Infinity Fabric Link (Compl. ¶¶31-32). The complaint includes a diagram illustrating the MI250X MCM architecture, which shows two GCDs, HBM2e memory stacks, and connections for Infinity Fabric (Compl. p. 10).

IV. Analysis of Infringement Allegations

11,550,512 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a router module comprising a host interface and a node interface, wherein the router module is communicatively coupled to the host compute system via the host interface The Infinity Fabric Link and its associated controller, which connects to a host CPU (e.g., EPYC) and controls data routing. ¶32 col. 9:4-9
a plurality of serially coupled compute nodes in an execution pipeline The two Graphic Compute Dies (GCDs) within a single MI200 Series Accelerator, which are alleged to be serially coupled via the In-package Infinity Fabric. ¶35 col. 3:31-35
each respective compute node ... comprising: a communications link, wherein the respective compute node is communicatively coupled to the node interface at the router module via the communications link either directly or indirectly via an adjacent compute node The internal Infinity Fabric within a GCD and the In-package Infinity Fabric connecting the two GCDs, which couple the GCDs to the node interface of the router module. ¶¶36-37 col. 3:36-40
a data store comprising records associated with a data processing operation The High Bandwidth Memory (HBM2e), which stores large datasets ("records") for data processing operations like HPC and AI workloads. ¶38 col. 3:41-43
a programmable logic component to execute the data processing operation in cooperation with the data store The Compute Units ("CU")/engines within each GCD, which receive data from the HBM2e memory to perform data processing. ¶39 col. 3:44-46
a node memory comprising data and instructions to support operation of the programmable logic component ... and to facilitate inter-node data communications The L2 cache and controller within each GCD, which contains data/instructions from HBM2e and facilitates inter-GCD communication via Infinity Fabric. ¶¶40-41 col. 3:47-52
a data mover component to facilitate intra-node data communications between the programmable logic component and the node memory A crossbar or bus that facilitates data communication between the Compute Units and the L2 cache within a single GCD. ¶44 col. 3:53-56
a storage interface component to facilitate intra-node data communications between the programmable logic component and the data store The memory controller within each GCD, which transfers data from the HBM2e data store to the GCD and its Compute Units. ¶45 col. 3:57-4:1
wherein the storage interface component utilizes a plurality of communications channels to transfer data The memory subsystem of a GCD is partitioned into 32 channels for transferring data from the HBM2e memory. ¶46 col. 4:5-9

Identified Points of Contention

  • Scope Questions: A central question may be whether the term "plurality," as used in "a plurality of serially coupled compute nodes," reads on an architecture with only two such nodes (the two GCDs). Further, the interpretation of "execution pipeline" will be critical, specifically whether the side-by-side coupling of two GCDs in a single package, as depicted in the complaint (Compl. p. 10), constitutes the tiered "pipeline" structure suggested by the patent's figures (’512 Patent, Fig. 1).
  • Technical Questions: The complaint identifies the "router module" as the "Infinity Fabric Link" and its controller (Compl. ¶32). A question for the court may be whether this distributed fabric and control logic constitutes the discrete "router module" element described and depicted in the patent (’512 Patent, Fig. 1, element 120).

11,886,750 Patent Infringement Allegations

The complaint incorporates by reference its allegations for the ’512 Patent to support infringement of most elements of the ’750 Patent's claim 1 (Compl. ¶¶56, 58-65). The primary distinction is the system topology.

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a router module comprising a host interface and a node interface The Infinity Fabric Link and its associated controller, which connects to a host CPU (e.g., EPYC) and controls data routing. (Incorporating by reference). ¶56 col. 54:49-52
multiple parallel first tier compute nodes coupled to one or more additional compute nodes in series Different topologies of MI200 Series Accelerators, such as the "Flagship ML Topology," where multiple accelerators (each containing a pair of serially-coupled GCDs) are connected in parallel. ¶57 col. 54:53-56
each compute node comprising: a communications link... a data store... a programmable logic component... a node memory... a data mover component... a storage interface component... The complaint alleges these elements are present in the Accused Products by incorporating by reference the same allegations made for the '512 patent. ¶¶58-65 col. 54:57- col. 55:12

Identified Points of Contention

  • Scope Questions: The primary point of contention will likely be the construction of "multiple parallel first tier compute nodes coupled to one or more additional compute nodes in series." The complaint supports this element with a diagram of a "Flagship ML Topology with MI250," which depicts a complex, ring-like network of multiple accelerators (Compl. p. 23). A question for the court will be whether this mesh-like topology can be construed to meet the specific parallel-then-serial hierarchy recited in the claim.
  • Technical Questions: Plaintiff's theory appears to map "nodes in series" to the two GCDs within a single accelerator, and "parallel first tier" nodes to multiple such accelerators working together (Compl. ¶¶57, 59). Whether this mapping reflects the actual technical operation and structure described in the patent will be a key factual question.

V. Key Claim Terms for Construction

For the ’512 Patent

  • The Term: "a plurality of serially coupled compute nodes in an execution pipeline"
  • Context and Importance: This term defines the core architecture of the claimed system. Its construction is critical because the infringement allegation hinges on whether a two-die GPU package constitutes such a structure. Practitioners may focus on whether "pipeline" requires more than two stages or a more distinct separation between nodes than exists between two GCDs on a single substrate.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent abstract refers generally to a "distributed hardware architecture" and mentions "one or more compute nodes," suggesting flexibility in implementation (’512 Patent, Abstract).
    • Evidence for a Narrower Interpretation: Figure 1 of the patent depicts "FIRST COMPUTE NODE TIER" and an arrow to/from "NEXT TIER," which may suggest a structure with more distinct, sequential stages than two co-packaged dies (’512 Patent, Fig. 1). The use of "plurality" may be argued to require more than two nodes.

For the ’750 Patent

  • The Term: "multiple parallel first tier compute nodes coupled to one or more additional compute nodes in series"
  • Context and Importance: This term dictates the specific parallel-serial topology of the system. The infringement case depends on whether AMD's multi-accelerator topologies, which the complaint shows as rings or meshes (Compl. p. 23), fit this structured definition.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent discloses a system for use in a "distributed processing environment or paradigm," which could support a broad reading of how nodes are interconnected (’750 Patent, col. 2:44-45).
    • Evidence for a Narrower Interpretation: The claim language itself is highly structured, suggesting a two-level hierarchy: a parallel "first tier" of nodes, each of which is then connected to a separate serial chain of "additional compute nodes." This may be argued to exclude architectures where all nodes are interconnected in a single, non-hierarchical mesh or ring.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement for all three patents-in-suit. The inducement allegations are based on AMD allegedly publishing and providing "marketing materials, technical specifications, whitepapers, datasheets, user manuals," which are claimed to instruct and encourage third parties to integrate and use the Accused Products in an infringing manner (Compl. ¶¶49, 68, 87). The contributory infringement allegations are based on the assertion that the Accused Products, particularly the GCDs, constitute a material part of the patented inventions, are not staple articles of commerce, and are especially made or adapted for infringement (Compl. ¶¶50, 69, 88).
  • Willful Infringement: Willfulness is alleged for all three patents based on AMD's knowledge of the patents and its alleged infringement "at least as of the filing of this Complaint" (Compl. ¶¶52, 71, 90). The complaint does not allege pre-suit knowledge.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can the architectural terms central to the asserted patents, such as an "execution pipeline" of "serially coupled compute nodes" ('512 Patent) and a "parallel first tier" of nodes each coupled to nodes "in series" ('750 Patent), be construed to cover the accused multi-die GPU and multi-accelerator ring topologies?
  • A key evidentiary question will be one of structural correspondence: does the technical evidence show that the accused AMD Instinct accelerators, with their co-packaged GCDs and Infinity Fabric interconnects, embody the specific, tiered hardware structures claimed in the patents, or is there a fundamental mismatch between the patent's prescribed architecture and the accused product's actual design?