Altair Logix LLC v. Toradex Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Altair Logix LLC (Texas)
  • Defendant: Toradex, Inc. (Washington)
  • Plaintiff’s Counsel: Mann Law Group PLLC
• Case Identification: 2:19-cv-00449, W.D. Wash., 03/27/2019
• Venue Allegations: Venue is alleged to be proper in the Western District of Washington because the Defendant is incorporated in Washington and has a business location within the district.
• Core Dispute: Plaintiff alleges that Defendant’s Apalis iMX6 computer-on-module products infringe a patent related to dynamically reconfigurable processor architectures for media processing.
• Technical Context: The technology concerns systems-on-a-chip (SoCs) with multiple, adaptive processing units designed to offer the performance of fixed-function hardware with greater flexibility and cost-efficiency.
• Key Procedural History: The complaint alleges that the asserted patent’s independent claim 1 was an originally filed claim that issued without any amendment or anticipation-based rejections during prosecution.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,289,434 - "Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates"

• Patent Identification: U.S. Patent No. 6,289,434, "Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates," issued September 11, 2001.

The Invention Explained

• Problem Addressed: The patent describes a technical challenge in integrated circuit design where conventional approaches represent a trade-off between performance and flexibility (’434 Patent, col. 1:42-49). Hard-wired, fixed-function circuits are fast but inflexible and exhibit "temporal redundancy" by dedicating silicon to all possible functions, even those not in use (’434 Patent, col. 2:50-57). Conversely, more flexible approaches like microprocessors, DSPs, and FPGAs often lack the cost-effectiveness or real-time performance for complex, parallel tasks like 3D graphics (’434 Patent, col. 2:1-33).
• The Patented Solution: The invention proposes an apparatus with multiple "media processing units" (MPUs) that can be adaptively and dynamically reconfigured at run-time (’434 Patent, col. 3:14-17). This architecture aims to reduce cost by removing redundancy through the re-use of computational and storage elements in different configurations, adapting the circuit to varying input data and processing needs without performance degradation (’434 Patent, col. 3:1-11). The system uses a memory-mapped architecture, depicted in Figure 3, for communication and control between the MPUs and other system components (’434 Patent, col. 4:26-37).
• Technical Importance: The described technology sought to provide a new paradigm for systems-on-a-chip capable of achieving the performance of fixed-function implementations at a lower cost by introducing dynamic reconfigurability (’434 Patent, col. 2:64-3:1).

Key Claims at a Glance

• The complaint directly asserts infringement of independent claim 1 (’434 Patent, col. 55:20-56:33; Compl. ¶27).
• The essential elements of independent claim 1 include:
  • An apparatus with an addressable memory and a plurality of media processing units.
  • Each media processing unit comprising: a multiplier, an arithmetic unit, an arithmetic logic unit (ALU), and a bit manipulation unit (BMU).
  • The ALU must be capable of operating concurrently with the multiplier and the arithmetic unit.
  • The BMU must be capable of operating concurrently with the ALU and at least one of the multiplier or arithmetic unit.
  • Each of the plurality of media processors is for performing at least one operation simultaneously with the performance of other operations by other media processing units.
  • Each operation comprises receiving an instruction and data from memory, processing the data to produce a result, and providing the result at the media processor input/output.
• The complaint’s prayer for relief broadly requests judgment on "one or more claims" but only provides specific infringement allegations for claim 1 (Compl. p. 29).

III. The Accused Instrumentality

Product Identification

• The "Accused Instrumentality" is identified as the Apalis iMX6 computer-on-module (Compl. ¶27).

Functionality and Market Context

• The complaint describes the Apalis iMX6 as a small form-factor computer-on-module based on the NXP i.MX 6 series of application processors, which feature multicore ARM Cortex-A9 processors (Compl. ¶¶28-29). The complaint alleges that each ARM core, which includes a NEON media coprocessor, functions as one of the claimed "media processing units" (Compl. ¶29). The NEON unit is described as an advanced SIMD (Single Instruction, Multiple Data) processing unit that is helpful for media processing, such as audio/video filters and codecs (Compl. ¶29, p. 15). A block diagram provided in the complaint shows the accused product's architecture, including a "Quad ARM® Cortex™-A9 Core" with "NEON per Core" and various "Media Processors" (Compl. ¶29, p. 14).
• The complaint alleges the product is marketed for a wide range of industrial applications, including automotive infotainment, industrial automation, avionics, and robotics (Compl. p. 12).

IV. Analysis of Infringement Allegations

'434 Patent Infringement Allegations

Identified Points of Contention

• Scope Questions: A principal question for the court will be whether a general-purpose ARM Cortex-A9 processor core with a NEON SIMD co-processor falls within the scope of the term "media processing unit" as described in the patent. The defense may argue that the patent's detailed description of a dynamically reconfigurable architecture limits the term to a structure different from a conventional superscalar processor, which the patent itself identifies as prior art to be improved upon.
• Technical Questions: What evidence does the complaint provide that the accused product's architecture performs the "adaptively dynamically reconfiguring [of] groups of computations and storage elements" that the patent specification describes as the core of the invention ('434 Patent, col. 3:14-17)? The infringement allegations focus on the presence of parallel functional units (multiplier, ALU, etc.), but the dispute may center on whether the accused product's operation is merely the execution of a conventional instruction set or the specific run-time reconfiguration of the hardware itself as taught by the patent.

V. Key Claim Terms for Construction

• The Term: "media processing unit"

• Context and Importance: This term is the lynchpin of the infringement case. Its construction will determine whether the accused product's ARM Cortex-A9 cores can be considered infringing structures. Practitioners may focus on this term because the patent specification heavily emphasizes a specific type of dynamically reconfigurable architecture, which may or may not be required by the plain language of the claim itself.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: Claim 1 defines the "media processing unit" by its required components (multiplier, arithmetic unit, ALU, BMU) and their concurrent operational capabilities, without explicitly reciting a "reconfiguration" limitation ('434 Patent, col. 55:31-56:20). A party could argue that any processor meeting these structural and functional requirements qualifies, regardless of the underlying architectural paradigm.
  • Evidence for a Narrower Interpretation: The specification repeatedly frames the invention as an apparatus for "adaptively dynamically reconfiguring groups of computations and storage elements in run-time" ('434 Patent, col. 3:14-17) to solve the problem of "temporal redundancy" inherent in prior art processors (’434 Patent, col. 2:50-53). A party could argue that the term "media processing unit" is implicitly limited by this extensive description of the invention's purpose and function, distinguishing it from a general-purpose processor.

• The Term: "capable of operating concurrently"

• Context and Importance: The claim requires concurrency between several of the MPU's internal components. The meaning of "concurrently" is critical, as it could distinguish between the standard parallel execution pathways in a modern processor and the specific, reconfigurable data routing taught in the patent.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The term could be construed to mean that the hardware architecture simply allows for the simultaneous or overlapping execution of instructions on different functional units (e.g., in a pipelined or superscalar manner), as is common in modern processors and which the diagrams in the complaint appear to show (Compl. ¶¶32-33).
  • Evidence for a Narrower Interpretation: The patent describes a specific "reconfigurable routing matrix" and memory-mapped protocol that enables its flexible data paths ('434 Patent, col. 4:38-51). A party might argue that "concurrently" should be read in light of this disclosed mechanism, requiring more than just the parallel execution units found in a conventional CPU.

VI. Other Allegations

• Indirect Infringement: The complaint does not contain counts for, or allege specific facts to support, indirect infringement.
• Willful Infringement: The complaint does not include an allegation of willful infringement. It alleges that Defendant has had "at least constructive notice of the '434 patent by operation of law" (Compl. ¶38).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the term "media processing unit," which is rooted in the patent's detailed disclosure of a dynamically reconfigurable architecture, be construed to cover a general-purpose ARM processor core with a standard SIMD coprocessor, an architecture the patent arguably positions itself as an improvement upon?
• A key evidentiary question will be one of operative functionality: does the accused product's architecture merely execute a conventional instruction stream using parallel hardware units, or does it embody the specific run-time reconfiguration of computational elements that the '434 patent describes as its fundamental solution to the problems of prior art processors? The case may turn on whether the accused product’s functionality matches the inventive concept described in the specification, beyond just the presence of the claimed structural components.