Altair Logix LLC v. Phytec America LLC

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Altair Logix LLC (Texas)
  • Defendant: Phytec America L.L.C. (Washington)
  • Plaintiff’s Counsel: Mann Law Group PLLC
• Case Identification: 2:19-cv-01933, W.D. Wash., 11/26/2019
• Venue Allegations: Venue is alleged to be proper based on Defendant being a Washington limited liability company with a place of business in the district, where acts of infringement have allegedly occurred.
• Core Dispute: Plaintiff alleges that Defendant’s phyFLEX-i.MX6 System-on-Module products infringe a patent related to dynamically reconfigurable circuits for processing data.
• Technical Context: The technology concerns processor architectures that aim to provide the performance of fixed-function hardware with the flexibility of reconfigurable circuits, a central theme in System-on-a-Chip (SoC) design.
• Key Procedural History: The complaint notes that the asserted independent claim, Claim 1 of the patent-in-suit, was an originally filed claim that issued without amendment and was not rejected as anticipated by any prior art during prosecution.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,289,434 - "Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates"

• Issued: September 11, 2001

The Invention Explained

• Problem Addressed: The patent addresses the trade-offs between high-performance but inflexible "hard-wired" integrated circuits and more flexible but lower-performing alternatives like microprocessors, DSPs, or FPGAs. Specifically, it identifies "temporal redundancy" in fixed-function systems, where silicon resources for all possible functions must be implemented even if they are not used for a given task (Compl. ¶¶14, 20; ’434 Patent, col. 2:50-57).
• The Patented Solution: The invention proposes an apparatus with multiple "media processing units" (MPUs) that can be dynamically reconfigured at run-time. This is intended to reduce cost and inefficiency by re-using computational and storage elements in different configurations to adapt to varying input data and processing requirements, thereby avoiding the need to implement all possible functionalities simultaneously (’434 Patent, col. 3:1-18). The overall architecture, shown in Figure 3, connects these MPUs through a pipelined communication protocol (’434 Patent, Fig. 3).
• Technical Importance: The technology sought to provide a new method for implementing systems on silicon that could achieve the performance of fixed-function hardware at a lower cost by removing redundancy through dynamic reconfiguration (Compl. ¶13; ’434 Patent, col. 2:64-3:11).

Key Claims at a Glance

• The complaint's infringement allegations focus exclusively on independent Claim 1 (Compl. ¶27).
• The essential elements of Claim 1 are:
  • An apparatus for processing data, comprising:
  • an addressable memory for storing the data, and a plurality of instructions, and having a plurality of input/outputs;
  • a plurality of media processing units, each media processing unit having an input/output coupled to the memory and comprising:
    • a multiplier having data, instruction, and output couplings;
    • an arithmetic unit having data, instruction, and output couplings;
    • an arithmetic logic unit having data, instruction, and output couplings, and being capable of operating concurrently with at least one selected from the multiplier and arithmetic unit; and
    • a bit manipulation unit having data, instruction, and output couplings, and being capable of operating concurrently with the arithmetic logic unit and at least one selected from the multiplier and arithmetic unit;
  • each of the plurality of media processors for performing at least one operation, simultaneously with the performance of other operations by other media processing units, where an operation comprises receiving an instruction and data from memory, processing the data, and providing a result.

III. The Accused Instrumentality

Product Identification

• The phyFLEX-i.MX6 System-on-Module ("SOM") (Compl. ¶27).

Functionality and Market Context

• The accused product is a compact hardware module designed for embedded systems, based on the Freescale (now NXP) i.MX6 family of application processors. The complaint alleges that the ARM Cortex-A9 Dual/Quad Core processors within the i.MX6 chip, each containing a NEON media coprocessor, constitute the "plurality of media processing units" (Compl. ¶29). The complaint provides a block diagram of the i.MX 6Quad processor, identifying the CPU platform with its multiple ARM cores as the "Media Processors" (Compl. p. 13). These processors are marketed for solutions ranging from "cost-efficiency to high demand performance at low power" for applications like media processing (Compl. ¶11).

IV. Analysis of Infringement Allegations

Claim Chart Summary

’434 Patent Infringement Allegations

Identified Points of Contention

• Scope Questions: A central question is whether a general-purpose ARM Cortex-A9 CPU core paired with a NEON SIMD (Single Instruction, Multiple Data) coprocessor constitutes the "media processing unit" described in the patent. The patent describes its MPUs as "virtually identical" RISC-like elements that are dynamically reconfigured at run-time to reduce "temporal redundancy," a specific architectural concept (’434 Patent, col. 2:50-53, 13:61-66). The complaint's mapping of claim elements to the accused hardware raises the question of whether the accused product's architecture aligns with this patented concept or represents a different technological approach.
• Technical Questions: The complaint alleges the NEON unit's components are "capable of operating concurrently" as required by the claim, supported by a block diagram of the NEON pipeline (Compl. p. 19). An evidentiary question may arise as to whether the standard operational parallelism within a SIMD pipeline meets the specific concurrency requirements taught in the patent, which describes executing "three concurrent 32 bit arithmetic or logical operations in parallel" in a single clock cycle (’434 Patent, col. 13:40-44).

V. Key Claim Terms for Construction

The Term: "media processing unit"

• Context and Importance: This term defines the fundamental building block of the claimed apparatus. The infringement case rests on construing this term to read on the accused product's ARM Cortex-A9 cores and their associated NEON coprocessors. Practitioners may focus on this term because the patent's description appears to teach a specific, reconfigurable architecture, while the accused product uses a more general-purpose CPU architecture.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent abstract describes an apparatus where processors "operate under control of a stored program, which configures each processor before or during operation" (’434 Patent, Abstract). The complaint cites the patent for the proposition that the term refers to the "aggregate of the dynamically reconfigurable computational and storage elements" (Compl. ¶22, citing ’434 Patent, col. 3:14-23).
  • Evidence for a Narrower Interpretation: The specification repeatedly emphasizes that the invention's purpose is to solve the problem of "temporal redundancy" in fixed-function systems through "adaptively dynamically reconfiguring groups of computational and storage elements in run-time" (’434 Patent, col. 2:50-53, 3:14-18). This could support an argument that a "media processing unit" must possess this specific run-time reconfiguration capability, not just be a powerful processor.

The Term: "capable of operating concurrently"

• Context and Importance: This functional limitation appears twice in Claim 1 and is critical to defining the operational relationship between the multiplier, arithmetic unit, arithmetic logic unit, and bit manipulation unit. The complaint alleges this functionality exists in the accused NEON coprocessor (Compl. ¶¶32, 33).
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The language "capable of" suggests a device need only have the ability, not that it must always be operating concurrently. Block diagrams showing parallel data paths could be cited to support this capability.
  • Evidence for a Narrower Interpretation: The specification provides a specific example of the claimed capability, stating an MPU may be configured "to execute three concurrent 32 bit arithmetic or logical operations in parallel while accessing four 32 bit data words from memory ... all this in a single clock cycle" (’434 Patent, col. 13:40-44). This passage may be used to argue for a specific, high degree of simultaneous operation as the required meaning of "concurrently."

VI. Other Allegations

• Indirect Infringement: The complaint does not include counts for indirect infringement (inducement or contributory infringement). The allegations are focused on direct infringement under 35 U.S.C. §271 (Compl. ¶¶1, 27).
• Willful Infringement: The complaint does not allege willful infringement or request enhanced damages. It alleges that Defendant had at least constructive notice of the ’434 Patent by operation of law (Compl. ¶38).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of architectural scope: Can the term "media processing unit," described in the patent as a specific, RISC-like, dynamically reconfigurable element designed to overcome "temporal redundancy," be construed to read on the accused architecture of a general-purpose ARM Cortex-A9 core with a NEON SIMD coprocessor? The case may turn on whether the accused product embodies the patent’s specific solution or represents a distinct technological paradigm.
• A key evidentiary question will be one of functional capability: Does the accused NEON coprocessor's standard pipeline parallelism satisfy the patent's requirement that its various functional units be "capable of operating concurrently"? The dispute will likely focus on whether this claim language requires a specific degree of simultaneous, independent operation as taught in the patent's detailed description, or if the inherent capabilities of the accused SIMD architecture suffice.