DCT
2:20-cv-01503
NXP USA Inc v. Impinj Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: NXP USA, Inc. (Delaware) and NXP BV. (Netherlands)
- Defendant: Impinj, Inc. (Delaware)
- Plaintiff’s Counsel: Richards, Layton & Finger; Jones Day
- Case Identification: 2:20-cv-01503, D. Del., 10/04/2019
- Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant Impinj, Inc. is a Delaware corporation.
- Core Dispute: Plaintiff alleges that Defendant’s UHF RFID tag chips, associated semiconductor wafers, and RFID reader products infringe a portfolio of eight U.S. patents concerning semiconductor wafer manufacturing, RFID circuit design, and communication protocols.
- Technical Context: The technology relates to the design and fabrication of semiconductor wafers for products like RFID tags, focusing on optimizing wafer layout and the design of internal power management and communication circuits.
- Key Procedural History: The provided documents indicate that after this complaint was filed, several asserted patents were subject to post-grant proceedings. U.S. Patent Nos. 6,680,523 and 6,819,092 had all claims cancelled in Inter Partes Review (IPR) proceedings. U.S. Patent No. 7,257,092 had its original claims cancelled and new claims added during an Ex Parte Reexamination. These subsequent events raise significant questions about the viability of the counts asserting these specific patents.
Case Timeline
| Date | Event |
|---|---|
| 2001-02-27 | U.S. Patent No. 6,680,523 Priority Date |
| 2001-03-13 | U.S. Patent No. 7,257,092 (Amtmann) Priority Date |
| 2001-10-09 | U.S. Patent No. 6,819,092 (Bretschneider) Priority Date |
| 2002-06-07 | U.S. Patent No. 7,374,097 Priority Date |
| 2003-12-23 | U.S. Patent No. 7,456,489 & 7,538,444 Priority Date |
| 2004-01-20 | U.S. Patent No. 6,680,523 Issue Date |
| 2004-11-16 | U.S. Patent No. 6,819,092 (Bretschneider) Issue Date |
| 2007-07-12 | U.S. Patent No. 8,415,769 Priority Date |
| 2007-08-14 | U.S. Patent No. 7,257,092 (Amtmann) Issue Date |
| 2007-11-30 | U.S. Patent No. 7,795,951 Priority Date |
| 2008-05-20 | U.S. Patent No. 7,374,097 Issue Date |
| 2008-11-25 | U.S. Patent No. 7,456,489 Issue Date |
| 2009-05-26 | U.S. Patent No. 7,538,444 Issue Date |
| 2010-09-14 | U.S. Patent No. 7,795,951 Issue Date |
| 2013-04-09 | U.S. Patent No. 8,415,769 Issue Date |
| 2019-10-04 | Complaint Filing Date |
| 2020-09-17 | IPR Filed for U.S. Patent No. 6,680,523 |
| 2020-10-05 | IPR Filed for U.S. Patent No. 6,819,092 (Bretschneider) |
| 2022-04-28 | Reexamination Request Filed for U.S. Patent No. 7,257,092 (Amtmann) |
| 2022-08-04 | IPR Certificate Issued for U.S. Patent No. 6,819,092 (claims cancelled) |
| 2022-08-15 | IPR Certificate Issued for U.S. Patent No. 6,680,523 (claims cancelled) |
| 2024-11-27 | Reexamination Certificate Issued for U.S. Patent No. 7,257,092 |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,680,523 - Semiconductor Wafer With Process Control Modules
Issued January 20, 2004
The Invention Explained
- Problem Addressed: The patent describes known methods for placing process control modules (PCMs) on semiconductor wafers as inefficient. Placing PCMs in special "drop-in" areas or within the "dicing paths" (the channels between chips) either consumes valuable wafer area or requires unnecessarily wide dicing paths, reducing the number of chips that can be fabricated on a single wafer (ʼ523 Patent, col. 1:11-35).
- The Patented Solution: The invention proposes arranging the PCMs within the standard grid of chips (the "exposure fields") by having a PCM occupy the space that would otherwise be used for a production chip (ʼ523 Patent, Abstract; col. 3:15-18). This allows for robust quality monitoring across the wafer without wasting space on widened dicing paths.
- Technical Importance: This method provided a way to integrate necessary quality-control structures onto a wafer with minimal impact on production yield, optimizing the use of expensive semiconductor real estate (ʼ523 Patent, col. 2:1-12).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶12).
- Essential elements of Claim 1:
- A semiconductor wafer having a multitude of chips, situated in a multitude of adjacent exposure fields.
- Process control modules which are each arranged in a given area on the wafer.
- The given areas are formed by the exposure fields.
- Each process control module takes the place of at least one chip.
U.S. Patent No. 7,456,489 - Wafer With Optical Control Modules In IC Fields
Issued November 25, 2008
The Invention Explained
- Problem Addressed: The patent identifies a problem in prior art wafer layouts where placing control module fields between adjacent chips leads to wide saw paths, which wastes wafer surface area and reduces manufacturing efficiency (ʼ489 Patent, col. 1:24-42).
- The Patented Solution: The invention solves this by arranging at least two control module fields within each exposure field to run parallel to the saw paths. Critically, each control module field is made up of multiple sections that are "distributed among several lattice fields," meaning the components of the control module are placed in unused areas within the footprint of multiple chips, rather than in a dedicated, separate area (ʼ489 Patent, Abstract; col. 2:9-18).
- Technical Importance: This technique allows for the integration of optical control modules needed for manufacturing alignment and testing while maintaining narrow saw paths, thereby maximizing the density of integrated circuits on the wafer (ʼ489 Patent, col. 2:19-27).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶18).
- Essential elements of Claim 1:
- A wafer comprising exposure fields where at least two control module fields are provided.
- Each control module field runs parallel to the first saw paths.
- Each control module field contains at least one optical control module with a plurality of components.
- Each control module field comprises a plurality of control module field sections and is distributed among several lattice fields.
- Each control module field section is located in a lattice field and contains at least one control module component.
U.S. Patent No. 7,538,444 - Wafer With Optical Control Modules In Exposure Fields
Issued May 26, 2009
- Technology Synopsis: This patent addresses a similar wafer layout problem. The solution involves providing at least two control module fields within each exposure field such that they "do not reside in any of the dicing paths" and are provided "in place of a preset number of lattice fields" at a specified average distance from one another (ʼ444 Patent, Abstract; Compl. ¶24).
- Asserted Claims: Independent claim 1 is asserted (Compl. ¶24).
- Accused Features: The layout of the semiconductor wafer for the Monza® 6 family of RFID tag chips, specifically the arrangement of its control module fields relative to dicing paths and lattice fields, is accused of infringement (Compl. ¶¶ 24-25).
U.S. Patent No. 8,415,769 - Integrated Circuits On A Wafer And Method For Separating Integrated Circuits On A Wafer
Issued April 9, 2013
- Technology Synopsis: This patent describes forming alignment marks from the same metallization layers used to create the integrated circuits themselves. These internal alignment marks are intended to be detectable from the bottom of the wafer to guide a laser or saw during the die separation process, improving alignment accuracy (ʼ769 Patent, Abstract).
- Asserted Claims: Independent claim 1 is asserted (Compl. ¶30).
- Accused Features: The integrated circuits on the Monza® R6 wafer are accused of infringing by allegedly having alignment marks that are formed from metallization layers used for the circuits, which are configured to align a separating device (Compl. ¶¶ 30-31).
U.S. Patent No. 7,795,951 - High-Dynamic Range Low Ripple Voltage Multiplier
Issued September 14, 2010
- Technology Synopsis: This patent discloses a voltage multiplier circuit, such as a charge pump for an RFID tag. The invention uses a feedback bias control circuit to regulate an input level regulator, which provides a stable voltage with low ripple over a wide dynamic range, based on a comparison between the output voltage and a reference voltage (ʼ951 Patent, Abstract). The "Monza R6 Tag Chip Block Diagram" in the complaint shows a "Power Management" block. (Compl. ¶36).
- Asserted Claims: Independent claim 1 is asserted (Compl. ¶37).
- Accused Features: The "Power Management functionality" within the Monza® R6 UHF RFID tag chips is alleged to contain a voltage multiplier circuit with the claimed feedback structure (Compl. ¶¶ 37-38).
U.S. Patent No. 7,257,092 - Method Of Communicating Between A Communication Station And At Least One Data Carrier
Issued August 14, 2007
- Technology Synopsis: This patent describes a method to accelerate RFID system performance. It combines the "inventorization" procedure (where a reader identifies which tags are present) with the transmission of useful data from the tag, so that both the tag's identity and its data are acquired in a single, more efficient process (ʼ092 Amtmann Patent, Abstract).
- Asserted Claims: Independent claims 7, 11, and 19 are asserted (Compl. ¶¶ 44, 46, 48).
- Accused Features: Defendant's "FastID™ inventory mode" is accused of infringement. The Speedway® and Indy® readers are accused of infringing the station claims, while the Monza® family of tags is accused of infringing the data carrier claims (Compl. ¶¶ 43, 46, 48).
U.S. Patent No. 6,819,092 - Digitally Switchable Current Source
Issued November 16, 2004
- Technology Synopsis: This invention relates to a circuit for a digitally switchable current source designed to prevent damaging current spikes during state transitions. It achieves this by using a specific arrangement of switching transistors and current source transistors such that the current flow remains constant during the digital switching operation (ʼ092 Bretschneider Patent, Abstract). The complaint's block diagram illustrates a "Power Management" function in the accused chip. (Compl. ¶54).
- Asserted Claims: Independent claim 1 is asserted (Compl. ¶55).
- Accused Features: The "Power Management functionality" in the Monza® R6 RFID tag chips is alleged to include a digitally switchable current source with the claimed transistor arrangement (Compl. ¶¶ 55-56).
U.S. Patent No. 7,374,097 - Data Carrier For Storing Information Represented By An Information Voltage
Issued May 20, 2008
- Technology Synopsis: This patent describes a circuit within a data carrier (like an RFID tag) that uses a capacitor to store information (e.g., an "inventoried flag"). The invention includes "voltage-raising means" (like a charge pump) to generate an information voltage that is higher than the control signal, allowing the information to be stored more robustly against leakage currents (ʼ097 Patent, Abstract). A block diagram of the accused chip is provided in the complaint. (Compl. ¶61).
- Asserted Claims: Independent claim 4 is asserted (Compl. ¶62).
- Accused Features: The Monza® R6 tag chips are accused of infringing by having a circuit that uses a capacitor to store an "inventoried flag" and includes functionality to raise the voltage of a control signal to generate the stored information voltage (Compl. ¶¶ 62-63).
III. The Accused Instrumentality
- Product Identification: The accused instrumentalities are Defendant’s Monza® 6 family of UHF RFID tag chips, the semiconductor wafers on which they are fabricated, the Indy® family of tag reader modules, and the Speedway® family of tag readers (Compl. ¶¶ 12, 18, 43).
- Functionality and Market Context:
- The complaint alleges that the accused products form a complete RFID system. The Monza® chips are passive tags that are powered by an RF field from a reader (Compl. ¶36). The Speedway® and Indy® products act as readers ("communication station") that perform inventory procedures to identify and communicate with the tags (Compl. ¶¶ 43-47).
- The technical functionality at issue spans from the physical layout of the semiconductor wafers to the specific design of power management and communication circuits within the chips and the protocols used for communication between chips and readers (Compl. ¶¶ 13, 38, 45). The complaint alleges that the "FastID™" feature is a specific mode of operation for inventory procedures (Compl. ¶43).
IV. Analysis of Infringement Allegations
U.S. Patent No. 6,680,523 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A semiconductor wafer (1) having a multitude of chips (5), of which chips (5) each one of a given number of chips (5) is situated in one of a multitude of adjacent exposure fields (2) | The Monza® R6 wafer has several dozen reticles (exposure fields), each of which contains over a thousand chips. | ¶13 | col. 3:1-5 |
| and having process control modules (4) which are each arranged in a given area on the semiconductor wafer (1) | The Monza® R6 wafer also has process control modules arranged in the corners of exposure fields. | ¶13 | col. 3:11-14 |
| in which the given areas are formed by the exposure fields (2) | The process control modules are arranged in corners of exposure fields, which are described as "areas formed by exposure fields." | ¶13 | col. 3:13-14 |
| and in which each process control module (4) takes the place of at least one chip (5). | The process control modules are arranged "such that each process control module takes the place of one chip." | ¶13 | col. 3:15-18 |
- Identified Points of Contention:
- Scope Questions: The primary dispute may center on the definition of "process control module." The complaint uses the term conclusorily. The court will have to determine what specific structures on the accused wafer constitute a "process control module" and whether they are used for process control as contemplated by the patent, which describes their use for detecting fabrication flaws ('523 Patent, col. 1:23-25).
- Technical Questions: A factual question will be whether the accused structures, which the complaint alleges are "in the corners of exposure fields," genuinely "take the place of at least one chip" as required by the claim, or if they are located in areas, such as dicing streets, that are not considered part of the chip area.
U.S. Patent No. 7,456,489 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| wherein in each exposure field at least two control module fields are provided, each of which control module fields runs parallel to the first direction and thus to the first saw paths | Each exposure field has two control module fields, which are parallel to each other and to one of the sets of saw paths. | ¶19 | col. 2:9-12 |
| wherein each control module field within an exposure field comprises a plurality of control module field sections and is distributed among several lattice fields | The accused wafers have control module fields with a "plurality of control module field sections, and is distributed among several lattice fields." | ¶19 | col. 2:15-17 |
| and wherein each control module field section is located in a lattice field and contains at least one control module component. | Each control module field section is located in a lattice field and contains at least one control module component. | ¶20 | col. 2:17-18 |
- Identified Points of Contention:
- Scope Questions: A central question will be the construction of "distributed among several lattice fields." This language suggests an intermingling of control module components within the area of what would otherwise be productive ICs. The case may turn on whether the accused layout meets this structural and spatial requirement.
- Technical Questions: Evidence will be required to demonstrate that the accused structures are in fact "control module field sections" and that they are "located in a lattice field" as claimed. Plaintiff must prove that these structures are not merely part of the IC's own circuitry or located in inter-chip regions.
V. Key Claim Terms for Construction
For the ʼ523 Patent:
- The Term: "process control module"
- Context and Importance: This term is foundational to the infringement allegation for the ʼ523 Patent. The case hinges on whether certain structures on Impinj's wafers meet this definition. Practitioners may focus on this term because its definition will determine whether the accused structures, which take the place of chips, are merely non-functional placeholders or serve the specific technical purpose required by the patent.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes the modules functionally, stating they can "detect or recognize flaws" or be used as a "coarse grating" for positioning a device, suggesting any structure serving such a quality-control or alignment function could be covered (ʼ523 Patent, col. 1:23-25; col. 2:18-19).
- Evidence for a Narrower Interpretation: The patent title and background focus on "process control," which may support a narrower construction limited to structures that monitor specific semiconductor manufacturing steps (e.g., layer thickness, etching quality), as opposed to more general alignment marks. The patent distinguishes itself from prior art "alignment markers" (ʼ523 Patent, col. 1:15-17).
For the ʼ489 Patent:
- The Term: "distributed among several lattice fields"
- Context and Importance: This limitation is critical for distinguishing the invention from prior art where control modules might occupy a single, contiguous block. Infringement depends on proving that the accused control module fields are fragmented into sections and interspersed across multiple chip areas ("lattice fields").
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A plaintiff might argue that any physical placement of control module sections within the boundaries of more than one lattice field satisfies this limitation, regardless of the pattern of distribution.
- Evidence for a Narrower Interpretation: The specification explains that these sections can be placed in an area of a lattice field where "the IC in the lattice field in question does not have any IC components" (ʼ489 Patent, col. 2:51-54). A defendant could argue this limits the scope to only those unused portions of a die, requiring proof that the accused sections are placed in such specific non-functional areas.
VI. Other Allegations
- Willful Infringement: The complaint does not contain an explicit allegation of willful infringement. It requests attorneys' fees under 35 U.S.C. § 285 but does not plead facts typically associated with willfulness, such as pre-suit knowledge of the patents or egregious conduct.
VII. Analyst’s Conclusion: Key Questions for the Case
Mootness and Claim Viability: A threshold question for the court will be the impact of the post-filing IPR and reexamination proceedings. With all asserted claims of the ʼ523 and ʼ092 Bretschneider patents cancelled, and the asserted claims of the ʼ092 Amtmann patent replaced, the counts related to these three patents may be moot or require substantial amendment, potentially narrowing the scope of the case significantly.
Definitional Scope in Wafer Layout: For the surviving wafer layout patents, the case will likely turn on claim construction. A core issue will be one of definitional scope: can the term "process control module" ('523 Patent) be construed to cover the accused structures on Impinj's wafers, and does the accused layout meet the specific spatial requirement of being "distributed among several lattice fields" ('489 Patent)?
Evidentiary Proof of Technical Operation: For the circuit and system patents, the dispute will focus on functional operation. The complaint's allegations closely track the claim language. A key evidentiary question will be whether the accused power management circuits and the "FastID™" communication protocol actually operate in the specific manner required by the detailed limitations of their respective claims, a point that will require extensive technical evidence beyond the block diagrams provided.