PTAB

IPR2012-00019

Intellectual Ventures Management LLC v. Xilinx Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Interposer for Redistributing Signals
  • Brief Description: The ’968 patent relates to a method for manufacturing an integrated circuit (IC) assembly that includes an interposer. This interposer is disposed inside the IC package between a die and the package substrate, where it provides signal redistribution and bypass capacitance.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1-5, 7-12, 14, and 15 by Siniaguine

  • Prior Art Relied Upon: Siniaguine (Patent 6,730,540)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Siniaguine discloses every limitation of the challenged claims. Siniaguine teaches a method for manufacturing semiconductor packages using a "semiconductor interposer" which Petitioner equated to the claimed "interposing structure." Petitioner asserted that Siniaguine’s figures show this interposer (320) positioned between an IC die (310) and a wiring substrate (330), fulfilling the core requirements of independent claims 1 and 9. Siniaguine’s disclosure of flip-chip bonding was argued to teach the claimed plurality of micro-bumps on the die aligning with landing pads on the package. The re-routing limitation was allegedly met by conductive lines (150) within Siniaguine's interposer.
    • For dependent claims, Petitioner contended Siniaguine explicitly teaches including "decoupling capacitors" (meeting the "bypass capacitor" limitation of claims 2, 7, and 14), forming the interposer from a semiconductor substrate with metal and dielectric layers that lack transistors or PN junctions (claim 4 and 11), and arranging bumps and pads in distinct patterns (claims 5 and 12).

Ground 2: Obviousness of Claims 6 and 13 over Siniaguine in view of Patel

  • Prior Art Relied Upon: Siniaguine (Patent 6,730,540) and Patel (Patent 6,469,908)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Siniaguine teaches all elements of base claims 1 and 9, as detailed in Ground 1. The additional limitation in dependent claims 6 and 13—that the interposing structure includes a layer of epoxy and fiberglass—is taught by Patel. Patel discloses a method for fabricating an interposer substrate using well-known PC board techniques, and explicitly teaches that the substrate can be an organic material such as "FR-4 epoxy-glass."
    • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) would combine the teachings of Siniaguine and Patel. The modification of Siniaguine's interposer to include an epoxy and fiberglass layer as taught by Patel would have been an "obvious to try" design choice. A POSITA would be choosing from a finite, known, and predictable set of substrate materials for IC packaging applications.
    • Expectation of Success: A POSITA would have a reasonable expectation of success in this combination because using standard PC board materials like epoxy-glass for interposer substrates was a common and well-understood practice for achieving predictable results in the field of IC packaging.

Ground 3: Anticipation of Claims 1-4, 7-11, 14, and 15 by Chakravorty ’034

  • Prior Art Relied Upon: Chakravorty ’034 (Patent 6,477,034)

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued Chakravorty ’034, which is directed to interposer substrates that provide capacitance, anticipates the claims. Petitioner mapped FIG. 1 of Chakravorty ’034 to show an interposer substrate (100) disposed between an IC die (300) and a package substrate (200). This reference allegedly discloses a plurality of conductive bumps (152, 154) on the die that align with a corresponding plurality of landing pads (162, 164) on the package substrate. The signal re-routing function was purportedly taught by an electrode region (144) within a conductive layer of the interposer.
    • For dependent claims, Petitioner argued that the internal parallel plate capacitor structure of Chakravorty ’034’s interposer inherently supplies bypass current as required by claims 2, 7, and 14. Further, the composition of the interposer from a base substrate layer with conductive and dielectric layers was asserted to meet the limitation of having no transistors or PN junctions (claims 4 and 11).

  • Additional Grounds: Petitioner asserted numerous additional grounds of unpatentability. These included obviousness challenges combining Chakravorty ’034 with Ma (Patent 6,423,570) for claims 5 and 12, and with Patel for claims 6 and 13. Further anticipation and obviousness grounds were based on Chakravorty ’419 (Patent 6,611,419) and Bohr (Patent 6,617,681), alone and in various combinations with Siniaguine, Patel, and Ma, relying on similar prior art mapping and combination rationales.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-15 of the ’968 patent as unpatentable.