PTAB

IPR2012-00020

Intellectual Ventures Management LLC v. Xilinx Inc

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1. Case Identification

2. Patent Overview

  • Title: Configuration of a Multi-Die Integrated Circuit
  • Brief Description: The ’897 patent relates to methods and systems for configuring multi-die programmable integrated circuits (ICs), such as Field Programmable Gate Arrays (FPGAs). The technology involves a master die receiving configuration data, determining which segments of the data are for itself and which are for a slave die, and distributing the appropriate segments accordingly.

3. Grounds for Unpatentability

Ground 1: Obviousness over Wennekamp - Claims 1-7 are obvious over Wennekamp.

  • Prior Art Relied Upon: Wennekamp (Patent 7,397,272).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Wennekamp teaches all limitations of independent claim 1. Wennekamp discloses a system for the parallel configuration of multiple programmable devices, designating one as a master and others as slaves. It describes a master device receiving a configuration bitstream from memory, which contains data for both the master and slave devices. The master device provides portions of this bitstream to the slave devices in a parallel daisy-chain configuration, inherently teaching the determination and distribution of master and slave data segments. Wennekamp also discloses determining if data is targeted for a downstream device and passing it along, mapping to the limitations regarding a second IC.
    • Motivation to Combine (for §103 grounds): Not applicable as this is a single-reference ground. Petitioner contended that Wennekamp’s disclosure of a master device configuring slave devices rendered the claimed method obvious.
    • Expectation of Success (for §103 grounds): Not applicable.

Ground 2: Obviousness over Wennekamp and Miller - Claims 1, 8, and 12-14 are obvious over Wennekamp in view of Miller.

  • Prior Art Relied Upon: Wennekamp (Patent 7,397,272) and Miller (Patent 7,827,336).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground asserted that Wennekamp taught the core method of claim 1 and the functional aspects of system claim 8, while Miller supplied the structural arrangement of multiple dies on an interposer. Specifically, Miller explicitly discloses a multi-chip module where a primary die and a secondary die are connected through an interposer. Petitioner argued that combining Miller’s physical multi-die-on-interposer structure with Wennekamp’s master-slave configuration logic would result in the system claimed in claim 8. The configuration bus recited in claim 8 was alleged to be taught by the parallel data bus in Wennekamp.
    • Motivation to Combine (for §103 grounds): A person of ordinary skill in the art (POSITA) would combine Wennekamp’s configuration method with Miller’s well-known multi-chip packaging technique to achieve improved performance, reduced routing path lengths, and better signal integrity, which are known benefits of placing multiple dies on a single interposer.
    • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success, as combining a known configuration protocol with a standard packaging technology involved predictable results.

Ground 3: Obviousness over Rally - Claims 1-3 and 5-7 are obvious over Rally.

  • Prior Art Relied Upon: Rally (Patent 7,702,893).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Rally, by itself, renders claim 1 obvious. Rally discloses a system with a master integrated circuit and multiple slave ICs that share memory. During initialization, the master IC loads its own data and also loads the memory addresses for the slave ICs. The master then provides these addresses to the respective slave ICs, enabling them to retrieve their own configuration data. Petitioner contended this process directly maps to claim 1’s steps of a master die receiving data, determining segments for itself (master initialization data) and a slave (slave memory addresses), and distributing the slave data. The use of a JTAG interface for communication between ICs further supported the claimed method.
    • Motivation to Combine (for §103 grounds): Not applicable as this is presented as a single-reference ground.
    • Expectation of Success (for §103 grounds): Not applicable.

  • Additional Grounds: Petitioner asserted numerous additional obviousness challenges. These included combining Wennekamp with Walstrum (Patent 7,671,624), which, similar to Miller, teaches connecting dies via an interposer. Other grounds combined Rally with either Miller or Walstrum to explicitly add the multi-die interposer structure to Rally's master-slave configuration system. Finally, for dependent claim 9, Petitioner combined Wennekamp/Rally and Miller/Walstrum with Siniaguine (Patent 6,730,540) to teach the use of configurable active circuitry on the interposer itself.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-9 and 12-14 of the ’897 patent as unpatentable.