PTAB

IPR2012-00033

Sony Corp v. Tessera Inc

Title: Method of Making a Compliant Multichip Package
Brief Description: The ’337 patent describes a method for fabricating stacked, multichip semiconductor packages. The method utilizes a flexible substrate, similar to that used in Tape Automated Bonding (TAB) processes, which has pre-formed, detachable conductive leads that are bent and bonded to contacts on the stacked chips.

Prior Art Relied Upon: Nishino I (JP Patent Publication No. H5-3284).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Nishino I teaches a method of making a stacked multichip package on a TAB substrate that is nearly identical to the embodiment in the ’337 patent. Nishino I discloses providing a TAB substrate with conductive leads, assembling a first chip onto the substrate, and assembling a second chip overlying the first. The key difference is that Nishino I connects the top chip to the substrate using wire bonds, not pre-existing flexible leads from the substrate itself.
- Key Aspects: This ground was presented as being dependent on the Patent Owner's broad litigation claim construction. Petitioner contended that if, as the Patent Owner argued in district court, the claims only require an electrical connection rather than a physical connection of pre-existing "said flexible leads," then Nishino I's use of wire bonds to establish that electrical connection anticipates every limitation of the challenged claims.

Prior Art Relied Upon: Nishino I (JP H5-3284) and DiStefano '036 (WO 1994/03036).
Core Argument for this Ground:
- Prior Art Mapping: This ground was presented as an alternative to Ground 1, assuming the Board adopted Petitioner’s narrower claim construction requiring physical connection of pre-formed leads. Nishino I teaches the base structure of a stacked package on a TAB substrate but uses wire bonds for the top chip. DiStefano ’036, which is incorporated by reference in the ’337 patent, explicitly teaches the exact bonding method claimed: using a bonding tool to push detachable, flexible leads through windows in a TAB substrate to physically connect them to chip contacts.
- Motivation to Combine: A POSITA would combine these references because Nishino I expressly suggests that its wire-bond connection could be replaced with a TAB process. DiStefano ’036 provides a known and improved TAB-based bonding method. The combination would involve the simple substitution of one known bonding technique (wire bonding) with another known, improved technique (DiStefano's detachable leads) to achieve a more efficient manufacturing process.
- Expectation of Success: A POSITA would have had a high expectation of success, as the combination merely applies a known bonding technique, taught by DiStefano for connecting chips to TAB substrates, to the known stacked-chip structure of Nishino I. The predictable result is an electrically connected multichip package.

Prior Art Relied Upon: Nishino II (JP Patent Publication No. H05-13664).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Nishino II discloses every element of the challenged claims. Nishino II describes a method of making a stacked multichip package by first attaching two semiconductor chips side-by-side on a single, long, flexible TAB tape. The tape, which serves as the claimed "substrate," includes pre-formed conductive traces and flexible leads. The package is then formed by folding the tape in a "hairpin" bend between the chips, which stacks one chip over the other. In the final structure, both chips are assembled with their front faces (containing contacts) facing the substrate, and the pre-existing leads on the substrate connect to the contacts of both chips, achieving the required interconnections.
Additional Grounds: Petitioner asserted an additional anticipation challenge against claims 27-28 based on Arita (JP 06-177322), contingent on the adoption of Patent Owner's broad litigation construction regarding the order of method steps and the definition of "providing" a substrate.

Order of Method Steps: Petitioner argued that the plain language of claim 27 requires step (a)—"providing a substrate having a plurality of...flexible leads"—to be performed chronologically before step (d)—"connecting said flexible leads to the contacts." This interpretation is based on the antecedent basis for "said flexible leads" and is consistent with the specification's sole embodiment, which uses a pre-fabricated TAB tape. Petitioner contended that the Patent Owner's contrary litigation position—that the steps can be performed in any order—is an improper attempt to broaden the claims to cover conventional wire-bonding processes where connecting wires are introduced as separate components after chip assembly.
"Leads" vs. "Traces": Petitioner argued that under the broadest reasonable interpretation consistent with the specification, "leads" and "traces" are not structurally distinct elements. Instead, they both refer to portions of the same unitary metal conductors etched onto the substrate. A "lead" is simply the functional term for a portion of a "trace" that is used for bonding to a chip contact.

Petitioner requests institution of IPR and cancellation of claims 27-29 and 39 of Patent 6,054,337 as unpatentable.