Synopsys Inc v. Mentor Graphics Corp

1. Case Identification

• Case #: IPR2012-00041
• Patent #: 6,947,882
• Filed: September 26, 2012
• Petitioner(s): Synopsys, Inc.
• Patent Owner(s): Mentor Graphics Corporation
• Challenged Claims: 1-14 and 17-20

2. Patent Overview

• Title: Regionally Time Multiplexed Emulation System
• Brief Description: The ’882 patent describes a system for emulating a circuit design using a plurality of reconfigurable logic devices, such as field programmable gate arrays (FPGAs). The system allegedly achieves novelty by using at least one user clock for the logic elements and at least one independent signal routing clock to time-multiplex the routing of signals between the FPGAs.

3. Grounds for Unpatentability

Ground 1: Claims 1-14 and 17-20 are anticipated by or obvious over '191, optionally in view of Chen.

• Prior Art Relied Upon: Sample (’191 patent) and Chen (Patent 5,475,830).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the ’191 patent, titled "Emulation System With Time Multiplexed Interconnect," discloses every element of the challenged claims. The ’191 patent teaches a hardware emulation system using FPGAs and reprogrammable interconnect devices to reduce hardware cost by time-multiplexing signals. Crucially, Petitioner asserted that ’191 discloses the alleged point of novelty: the use of independent clocks. Specifically, ’191 describes a "High Speed Asynchronous Clock Signal" for the interconnect that "need not be synchronized" with other system clocks, as well as distinct user clocks for the logic devices. To the extent any element was not explicitly disclosed, Petitioner argued it would have been obvious in view of ’191.
  • Motivation to Combine (for §103 grounds): Petitioner contended that the ’191 patent explicitly incorporates the Chen patent by reference. This incorporation provided a direct motivation for a person of ordinary skill in the art (POSITA) to combine their teachings. Chen was cited for its detailed disclosure of asynchronous clocking, stating that "any pair of clock signals from different clock trees are assumed 'asynchronous'," thereby reinforcing the teachings of independent clock domains found in ’191.
  • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success because combining the explicit teachings of asynchronous clocking from Chen with the emulation system of ’191 (which already incorporated Chen) was a straightforward application of known principles.

Ground 2: Claims 5-8 and 17-20 are anticipated by or obvious over '760.

• Prior Art Relied Upon: Sample (’760 patent).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the ’760 patent, which was not considered during prosecution, anticipates or renders obvious the challenged claims. The ’760 patent describes flexible input/output (I/O) buffer circuits for FPGAs used in hardware emulation systems. It teaches time-multiplexing signals bidirectionally over a single I/O pin. Petitioner asserted that ’760 explicitly discloses using "two distinct clock signals" (I/O CLK(0) and I/O CLK(1)) that are globally distributed for routing signals between FPGAs, and that the time-multiplexing is "completely asynchronous relative to the timing of the A and B signals" being processed within the logic core, thus teaching independent user and routing clocks.

Ground 3: Claims 5-8, 17, and 20 are anticipated by or obvious over Agarwal.

• Prior Art Relied Upon: Agarwal (Patent 5,761,484).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Agarwal, which was listed on the face of the ’882 patent but not used in a rejection, anticipates or renders obvious the challenged claims. Agarwal teaches "Virtual Interconnections for Reconfigurable Logic Systems" to overcome pin limitations in FPGA-based logic emulation. It discloses multiplexing multiple logical wires over a single physical wire "at the maximum clocking frequency." Petitioner contended that Agarwal teaches two distinct clocking domains: an "emulation clock" corresponding to the user clock for the logic design being emulated, and a faster "pipeline clock" that operates at the maximum frequency of the FPGA to clock the physical wires (interconnects), thereby disclosing independent clocking for logic and routing.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that institution should not be precluded even though the ’191 patent was considered during prosecution. The argument was that the petition presented this "old art" in a new light. During prosecution, the examiner’s rejection over ’191 focused on claims related to "bi-directional data transfer," not clocking. In contrast, the petition’s challenge was centered on the various "clocking" limitations, which Petitioner argued were not the focus of the examiner's prior review. Furthermore, the petition introduced Chen, which was not cited during prosecution, to further illuminate the teachings of asynchronous clocking in the art and as incorporated into ’191.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-14 and 17-20 of the ’882 patent as unpatentable under 35 U.S.C. §§ 102 and/or 103.