Synopsys Inc v. Mentor Graphics Corp

1. Case Identification

• Case #: IPR2012-00042
• Patent #: 6,240,376
• Filed: September 26, 2012
• Petitioner(s): Synopsys, Inc.
• Patent Owner(s): Mentor Graphics Corporation
• Challenged Claims: 1-15 and 20-33

2. Patent Overview

• Title: Method and Apparatus for Gate-Level Simulation of Synthesized Register Transfer Level Designs with Source-Level Debugging
• Brief Description: The ’376 patent discloses methods for debugging synthesized circuit designs. It describes "instrumenting" register transfer level (RTL) source code by adding logic that, when synthesized into a gate-level design, provides signals indicating the execution status of specific source code statements, thereby enabling source-level debugging of the gate-level simulation.

3. Grounds for Unpatentability

Ground 1: Anticipation by Koch - Claims 1-5, 8-10, 20-24, 28, and 32-33 are anticipated by Koch.

• Prior Art Relied Upon: Koch (a 1996 article titled “Breakpoints and Breakpoint Detection in Source Level Emulation”).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Koch teaches a “source level emulation” (SLE) method that analyzes gate-level designs while maintaining a direct correlation to the VHDL (RTL) source code. The method involves identifying a statement in the source code, such as a specific operation, which serves as a breakpoint. Koch then describes synthesizing the source code into a gate-level design that includes hardware to detect when that breakpoint is reached. The system generates instrumentation signals, such as breakpoint identifiers from a finite state machine (FSM) or readable register values, which indicate the execution status of the source-level statements. Petitioner asserted this process directly reads on the claimed method of identifying a synthesizable RTL statement and synthesizing the source code into a gate-level netlist containing an instrumentation signal indicative of that statement's execution status.

Ground 2: Anticipation by Gregory - Claims 1-9, 11-14, 24-25, and 28-33 are anticipated by Gregory.

• Prior Art Relied Upon: Gregory (Patent 6,132,109).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended that Gregory discloses a debugging method where a designer inserts "probes" via a text phrase into RTL source code at locations intended for debugging. A translator tool synthesizes this marked-up code into a gate-level design. Gregory explicitly teaches that the translator adds components corresponding to the probes and interjects information into the netlist to prevent the optimizer from removing them. These preserved components provide instrumentation signals (e.g., temp_out signals) that are directly and traceably related back to the original probe statements in the source HDL. This allows for analysis of the gate-level circuit at the source-code level, which Petitioner argued fully discloses the limitations of the challenged claims.

Ground 3: Obviousness over Koch in view of 1995 Koch - Claims 11, and 25-27 are obvious over Koch in view of 1995 Koch.

• Prior Art Relied Upon: Koch (1996 article) and 1995 Koch (a 1995 article titled “Debugging of Behavioral VHDL Specifications by Source Level Emulation”).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that Koch teaches the base methods of claims 5 and 24, which involve creating and synthesizing instrumentation signals. The further limitations in claims 11 and 25 require displaying the source code and highlighting a specific statement when its corresponding instrumentation signal changes to a predetermined value. While the primary Koch reference focuses on breakpoint detection, the 1995 Koch reference, which describes a related SLE system, explicitly illustrates a user interface that provides graphical feedback by highlighting statements in the hardware description language (HDL) during emulation.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine the teachings because both references address the same problem of source-level debugging for emulated hardware and describe complementary aspects of an SLE system. Adding the graphical highlighting feature from 1995 Koch to the breakpoint detection system of Koch would be a simple, intuitive improvement to enhance usability by providing clear visual feedback to the designer.
  • Expectation of Success: A POSITA would have a high expectation of success, as integrating a graphical user interface to visually indicate the status of an internal signal was a well-known and routine practice in debugging and software development tools at the time.

• Additional Grounds: Petitioner asserted further anticipation and obviousness challenges. These included claims being anticipated by the HDL-ICE Brochure (a product brochure for an ASIC Emulation System) and Sample (Patent 5,960,191), both related to the commercial HDL-ICE system which predated the ’376 patent. Additional obviousness grounds were asserted based on Gregory and Sample in view of 1995 Koch, relying on similar motivations to add graphical feedback and enhanced debugging features.

4. Relief Requested

• Petitioner requests the institution of an inter partes review and the cancellation of claims 1-15 and 20-33 of the ’376 patent as unpatentable.