PTAB

IPR2013-00065

ChiMei Innolux Corp v. Semiconductor Energy Laboratory Co Ltd

Title: Electro-Optical Device and Thin Film Transistor and Method for Forming the Same
Brief Description: The ’311 patent discloses a method for fabricating a thin-film transistor (TFT). The invention centers on creating a specific "step-like" structure where an upper portion of the source and drain regions extends beyond a lower portion of the source and drain electrodes, allowing for subsequent laser irradiation to crystallize the channel region and activate ohmic contacts.

Prior Art Relied Upon: Taniguchi (Japanese Patent Publication No. JP H2-234125), Mori (Patent 5,270,567), and Van Zant (Microchip Fabrication: A Practical Guide to Semiconductor Processing, 2nd ed. 1990).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Taniguchi taught a complete method for manufacturing a TFT that met most claim limitations. However, Petitioner asserted Taniguchi failed to disclose the claimed "step-like" structure. This limitation was allegedly taught by Mori, which explicitly discloses a structure with source/drain regions extending beyond the electrodes. Van Zant was cited to demonstrate that other process steps, like overetching, were well-known to a person of ordinary skill in the art (POSA).
- Motivation to Combine: A POSITA would combine Taniguchi with Mori because Mori expressly teaches that its step-like structure reduces or eliminates gate-to-source and gate-to-drain capacitance problems. Incorporating this known solution for a known problem into Taniguchi’s TFT design would have been a predictable improvement.
- Expectation of Success: A POSITA would have had a high expectation of success, as the combination involved applying a known structural solution (from Mori) to a standard TFT fabrication process (from Taniguchi) using conventional and predictable semiconductor manufacturing techniques.

Prior Art Relied Upon: Noguchi (Japanese Patent Publication No. JP H1-144682), Mori (Patent 5,270,567), Kwasnick (Patent 5,198,694), and Van Zant (Microchip Fabrication: A Practical Guide to Semiconductor Processing, 2nd ed. 1990).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner contended that Noguchi disclosed a TFT manufacturing method nearly identical to that claimed in the ’311 patent but lacked the specific step-like electrode structure. As in the first ground, Mori was cited to supply this missing element. The Kwasnick reference was introduced to teach additional claimed features not found in Noguchi, such as forming a passivation layer over the transistor to create improved source/drain contacts.
- Motivation to Combine: A POSITA would be motivated to combine Noguchi's base process with Mori's structure to gain the known benefit of reduced capacitance. Likewise, a POSITA would be motivated to incorporate Kwasnick's teachings to add a protective passivation layer, a common and known improvement for enhancing device reliability and performance.

Prior Art Relied Upon: Matsuzaki (Japanese Patent Publication No. H1-180523), Mori (Patent 5,270,567), Kwasnick (Patent 5,198,694), and Van Zant (Microchip Fabrication: A Practical Guide to Semiconductor Processing, 2nd ed. 1990).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Matsuzaki, unlike the other primary references, explicitly disclosed a step-like TFT structure. Matsuzaki taught creating this structure for the stated purpose of preventing the undercutting of source and drain regions during etching. Mori was cited as further evidence of the known benefits of such a structure, reinforcing the motivation to use it. Kwasnick and Van Zant were again cited to supply teachings related to passivation layers and standard etching processes, respectively.
- Motivation to Combine: The motivation to create the claimed structure was derived directly from Matsuzaki’s explicit teaching to solve the problem of undercutting. A POSITA would further be motivated by Mori’s disclosure of the same structure for reducing capacitance, viewing it as a desirable design choice with multiple known advantages.
Additional Grounds: Petitioner asserted additional obviousness challenges against various claim groups using permutations of the same core prior art references, relying on similar motivations to combine and theories of unpatentability.

Petitioner stated that for the purposes of the inter partes review (IPR), claim terms should be afforded their ordinary and customary meaning.
The petition specifically addressed the term "overetching," arguing it is a common and well-understood term in semiconductor processing. Petitioner cited a claim construction order from a related district court case involving a sibling patent (Patent 6,756,258), where it was determined that "the process of overetching... [i]s well known as part of every etching process." Petitioner asserted this construction was binding on the identical term in the ’311 patent, given the common specification.

A central argument of the petition was that the ’311 patent is merely an obvious variant of a related, earlier-prosecuted patent, Patent 6,756,258, which shares a common specification and priority date.
Petitioner advanced a theory of administrative estoppel, arguing that the Patent Owner had previously surrendered or lost claims in an inter partes reexamination of the ’258 patent. Petitioner contended that the challenged claims of the ’311 patent are patentably indistinct from those cancelled or disclaimed claims in the ’258 patent, differing only in minor terminological variations. Therefore, Petitioner argued the Patent Owner should be estopped from re-litigating the patentability of the same subject matter.

Petitioner requested the institution of an IPR and the cancellation of claims 23-24, 26-40, 42-44, 46, 49-50, and 53-54 of Patent 7,923,311 as unpatentable under 35 U.S.C. §103.