PTAB

IPR2013-00065

Chimei Innolux Corp v. Semiconductor Energy Laboratory Co Ltd

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1. Case Identification

2. Patent Overview

  • Title: Electro-Optical Device and Thin Film Transistor and Method for Forming the Same
  • Brief Description: The ’311 patent discloses methods for fabricating a thin-film transistor (TFT). The invention is directed at a TFT structure and manufacturing process where crystallization of the channel formation region and activation of ohmic contacts occur via laser irradiation after the primary device structure is completed. A key feature is a "step-like" structure where an upper portion of the source and drain regions extends beyond a lower portion of the corresponding source and drain electrodes.

3. Grounds for Unpatentability

Ground 1: Obviousness over Taniguchi, Mori, and Van Zant - Claims including 23, 24, 26-28, 30-32, 34-36, 38-40 are obvious over Taniguchi in view of Mori and Van Zant.

  • Prior Art Relied Upon: Taniguchi (Japanese Publication # JP H2-234125), Mori (Patent 5,270,567), and Van Zant (a 1990 textbook on microchip fabrication).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Taniguchi taught a conventional method of manufacturing a liquid crystal display device containing a TFT, disclosing most of the claimed structural layers and process steps. The key limitation not explicitly shown in Taniguchi—the "step-like" structure where source and drain regions extend beyond the electrodes—was asserted to be expressly taught by Mori. Van Zant was cited as a general reference teaching well-known semiconductor processing techniques, such as isotropic etching, that a person of ordinary skill in the art (POSITA) would use to create the claimed structures.
    • Motivation to Combine: A POSITA would combine Mori's step-like structure with Taniguchi's TFT design to solve a known problem in the field. Mori explicitly taught that its structure reduces or eliminates parasitic gate-to-source and gate-to-drain capacitance, providing a clear reason to modify Taniguchi's design to achieve this known benefit.
    • Expectation of Success: Petitioner asserted a high expectation of success, as the combination involved applying a known structural solution (from Mori) to address a well-understood problem (parasitic capacitance) in a standard device architecture (from Taniguchi) using conventional fabrication methods (from Van Zant).

Ground 2: Obviousness over Noguchi, Mori, Kwasnick, and Van Zant - Claims including 29, 33, and 37 are obvious over Noguchi in view of Mori, Kwasnick, and Van Zant.

  • Prior Art Relied Upon: Noguchi (Japanese Publication # JP H1-144682), Mori (Patent 5,270,567), Kwasnick (Patent 5,198,694), and Van Zant.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Noguchi disclosed a method for manufacturing a TFT that was nearly identical to the process claimed in the ’311 patent, including the formation of the various semiconductor and conductive layers. However, to the extent Noguchi did not explicitly show the claimed step-like source and drain structure, Mori was again relied upon for this teaching. For dependent claims requiring a passivation layer covering portions of the substrate, Kwasnick was cited for its disclosure of forming such protective layers over TFTs.
    • Motivation to Combine: The primary motivation argued was to improve the performance of Noguchi’s TFT. A POSITA would have been motivated to incorporate the step structure from Mori into the Noguchi design to gain the known benefit of reduced parasitic capacitance, viewing it as a predictable and advantageous modification. Kwasnick provided a known solution for device protection.
    • Expectation of Success: The combination of these references was presented as a straightforward application of known design principles. Combining Mori's structure with Noguchi's process would have been a predictable integration of complementary technologies.

Ground 3: Obviousness over Matsuzaki, Mori, Kwasnick, and Van Zant - All Asserted Claims are obvious over Matsuzaki in view of Mori, Kwasnick, and Van Zant.

  • Prior Art Relied Upon: Matsuzaki (Japanese Publication # JP H1-180523), Mori (Patent 5,270,567), Kwasnick (Patent 5,198,694), and Van Zant.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Matsuzaki, the primary reference in this ground, itself disclosed a TFT manufacturing method that created the claimed step-like structure. Matsuzaki taught forming an upper portion of the source/drain regions that extends beyond the lower portion of the source/drain electrodes. Mori was cited as secondary support, reinforcing the known benefits of this specific structure. Kwasnick and Van Zant were again used to teach additional features like passivation layers and standard etching processes, respectively.
    • Motivation to Combine: Matsuzaki explicitly provided a motivation for its structure: preventing undercutting of the source and drain regions during the etching process. A POSITA would combine Matsuzaki's teachings with the general knowledge in the art (represented by Mori, Kwasnick, and Van Zant) to create a robust and reliable TFT. The motivation was to improve manufacturing yield and device performance simultaneously by using known, advantageous techniques.
    • Expectation of Success: Success would have been expected because Matsuzaki already taught the core claimed structure and provided a compelling reason for its use. Combining this with other conventional features like passivation was a routine design choice for a POSITA.

4. Key Claim Construction Positions

  • Petitioner asserted that claim terms should be given their ordinary and customary meaning.
  • The term "overetching" was highlighted as a critical limitation. Petitioner argued it refers to a conventional semiconductor process well known long before the ’311 patent's filing date. This position was supported by citing a claim construction order from a district court case involving a related patent (Patent 6,756,258), where the court determined that the "process of overetching... is well known as part of every etching process."

5. Relief Requested

  • Petitioner requested the institution of an inter partes review (IPR) and the cancellation of claims 23, 24, 26-40, 42-44, 46, 49, 50, 53, and 54 of Patent 7,923,311 as unpatentable under 35 U.S.C. §103.