PTAB

IPR2014-00104

Macronix Intl Co Ltd v. Spansion LLC

Key Events

Petition

petition

Title: Method for Electrically Interconnecting Periphery Area in Flash Memory
Brief Description: The ’625 patent discloses a method for fabricating semiconductor devices, specifically using a three-metal-layer process to interconnect electrical components in the periphery area of a memory device. The process aims to optimize layout density by defining specific orientations for the metal layers relative to each other.

Prior Art Relied Upon: Kuge (Patent 5,847,420), referred to as the '420 reference.
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that the ’420 reference, which describes a three-metal-layer process for the periphery area of a DRAM device, disclosed every limitation of the challenged claims. Kuge taught forming functional blocks (sub-circuits) by partially connecting components with a first metal layer and completing the sub-circuits with a second metal layer oriented substantially perpendicular to the first. Kuge further disclosed using a third metal layer, or "Main Bus," to interconnect these sub-circuits, with an orientation parallel to the first metal layer. This mapping was asserted to satisfy the limitations of independent claims 1, 6, and 10, as well as the dependent claims which recite features like dielectric layers and vias, also shown in Kuge.

Prior Art Relied Upon: Kuge (’420 patent) and Suzuki (Japanese Patent Application No. H11-68066), referred to as the '066 reference.
Core Argument for this Ground:
- Prior Art Mapping: This ground was presented as an alternative in the event the claims were construed as being limited to flash memory. Petitioner argued that Kuge taught all elements of the claimed three-metal process, but in the context of a DRAM device. The '066 reference described a similar three-metal interconnect structure for the periphery of a memory device.
- Motivation to Combine: The '066 reference expressly stated that while its primary embodiment was DRAM, the technology could be applied to other memory devices, including SRAM and flash memory. Petitioner contended a POSITA would thus be motivated to apply the specific, well-defined three-metal process from Kuge to a flash memory architecture, as suggested by Suzuki, to achieve the known benefits of improved layout density in that context.
- Expectation of Success: A POSITA would have a reasonable expectation of success because applying known metallization and layout techniques across different, yet fundamentally similar, memory technologies like DRAM and flash was a common and predictable practice in semiconductor design.

Prior Art Relied Upon: How et al. (Patent 6,242,767), referred to as the '767 reference.
Core Argument for this Ground:
- Prior Art Mapping: Petitioner asserted that the ’767 reference, which discloses a customizable routing architecture for an Application-Specific Integrated Circuit (ASIC), anticipated all challenged claims. How taught using lower metal layers (e.g., M1 and M2) for fixed, local interconnections within functional blocks (sub-circuits) and upper metal layers (e.g., M3 and M4) for routing between these blocks. How specified that its architecture could be used in periphery circuitry and that its functional blocks could be configured for memory functions. The reference also disclosed the perpendicular relationship between M1 (horizontal) and M2 (vertical) and the use of a third metal layer to interconnect the blocks, thereby teaching all key limitations of the independent claims.
Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 1-3 and 5 are obvious over Suzuki alone, and that claims 4 and 6-14 are obvious over Suzuki in view of Kuge. These arguments relied on similar rationales that the references collectively taught all claimed elements and a POSITA would have found it obvious to arrange them as claimed.

"periphery of a silicon substrate": Petitioner proposed the construction "an area on a silicon substrate outside a core area." This construction was argued to be consistent with the specification and was important for distinguishing the invention from prior art focused solely on the layout of core memory cell arrays.
"partially electrically interconnecting": Petitioner proposed the construction "electrically interconnecting said circuit components to some extent." This construction was based on the plain and ordinary meaning of the term "partially."
Preambles of Claims 1, 6, and 10: Petitioner argued that the preambles, which recite "flash memory," are not limiting. This position was asserted to broaden the scope of the claims beyond a specific memory type, thereby encompassing prior art directed to other memory devices like DRAM or general ASIC architectures.

Petitioner requested institution of an inter partes review and cancellation of claims 1-14 of the ’625 patent as unpatentable.