PTAB

IPR2014-00467

ARM Inc v. Vantage Point Technology Inc

Key Events

Petition

petition

Title: Method and Apparatus for Translating Virtual Addresses in a Data Processing System Having Multiple Instruction Pipelines and Separate TLB's for Each Pipeline
Brief Description: The ’750 patent relates to computer memory access techniques, specifically disclosing a data processing system with multiple instruction pipelines where each pipeline has its own separate translation look-aside buffer (TLB) for translating virtual memory addresses.

Prior Art Relied Upon: VAX 8800 (“Digital Technical Journal,” Number 4, Feb. 1987).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that the VAX 8800 reference describes a shared-memory multiprocessor system that anticipates every element of claims 1 and 8. The system consists of two identical processors, each constituting a separate, five-stage instruction pipeline. Each processor contains a "C Box" that provides address translation via a "Translation Buffer" (TB), which Petitioner asserted is a TLB. The system's use of two processors, each with its own pipeline and associated TB, allegedly maps directly to the claimed "first and second instruction pipeline" each with its own translation buffer. Petitioner further mapped the system's main memory page tables to the "master translation memory" limitation and the combination of hardware and microcode that handles a TB miss to the "direct address translation unit."
- Key Aspects: This ground asserted a direct, one-to-one correspondence between a commercially produced, well-documented prior art system and the challenged claims.

Prior Art Relied Upon: VAX 8800 and Patent 4,933,835.
Core Argument for this Ground:
- Prior Art Mapping: Petitioner contended that to the extent the VAX 8800 reference was deemed to be missing any specific structural or functional element of the claimed TLB, the ’835 patent necessarily supplied it. The ’835 patent, which details a TLB subsystem, was argued to teach all the specific TLB-related structures recited in the claims.
- Motivation to Combine: Petitioner's central motivation argument was based on prosecution history estoppel. During the original prosecution of the ’750 patent, the applicant relied on the ’835 patent to overcome an enablement rejection, arguing that the TLB structures ("address translators") were well-known and could be constructed in accordance with the ’835 patent. Petitioner argued this was a concession that the ’835 patent teaches the claimed structures. Therefore, a person of ordinary skill in the art (POSITA) would have been motivated to implement the known multiprocessor, multi-pipeline architecture of the VAX 8800 using the well-understood TLB structure from the ’835 patent, a simple substitution of one known element for another to achieve a predictable result.
- Expectation of Success: A POSITA would have a high expectation of success, as combining a standard processor architecture with a standard TLB design was a common practice in computer architecture.

Prior Art Relied Upon: Patent 4,920,477.
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued the ’477 patent, which describes a data processor for a Multiflow "Trace" computer, discloses a system with multiple instruction pipelines, each with its own TLB. The ’477 patent’s architecture includes multiple "clusters," each containing an "integer processor" that functions as an instruction pipeline. Critically, each of these integer processors is disclosed as having its own data TLB (DTLB). Petitioner asserted that this arrangement of multiple, distinct pipelines, each with its own dedicated TLB for address translation, all receiving instructions from a common instruction issuing unit, directly anticipated the apparatus of claim 1 and the corresponding method of claim 8.
Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 1 and 8 are obvious over the ’477 patent in view of Colwell (an IEEE article describing the same "Trace" architecture) and also over the ’477 patent in view of Colwell and the ’835 patent, relying on similar substitution and design choice rationales.

"a first and a second instruction pipeline": Petitioner proposed this term be construed as "Instruction execution units which receive instructions from a common instruction issuing unit." This construction was based on the patent's specification and was argued to be critical for showing that prior art multiprocessor systems, like the VAX 8800, meet the limitation.
"the first address translation unit": Petitioner argued this term, used in claim 1, lacked antecedent basis and was insolubly ambiguous. For the purpose of the IPR, Petitioner proposed two alternative constructions based on similar-sounding terms in the claim: (a) "the direct address translation unit" or (b) "the first address translator." Petitioner contended the claims were invalid under either construction, addressing both possibilities in its invalidity analysis. This ambiguity was presented as a central issue for interpreting the claim scope.

Petitioner requests institution of inter partes review and cancellation of claims 1 and 8 of Patent 5,463,750 as unpatentable.