PTAB

IPR2014-00882

Diablo Technologies Inc v. Netlist Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Circuit Providing Load Isolation And Memory Domain Translation For Memory Module
  • Brief Description: The ’150 patent discloses a circuit for a memory module designed to interface with a computer system's memory controller. The circuit isolates the electrical loads of memory devices on the module from the system and translates between a "system memory domain" (how the system perceives the memory) and the "physical memory domain" (the actual hardware configuration on the module).

3. Grounds for Unpatentability

Ground 1: Obviousness over Amidi and Klein - Claims 15-17, 22, 24, 26, and 31-33 are obvious over Amidi in view of Klein.

  • Prior Art Relied Upon: Amidi (Application # 2006/0117152) and Klein (Application # 2001/0008006).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Amidi disclosed the core architecture of the challenged claims. Amidi taught a "transparent four rank DDR memory module" that appears as a standard two-rank module to the system. It included a circuit with a CPLD (a logic element), a register, and a phase-lock loop (PLL) mounted on the module. Amidi's circuit received input signals (address, command, chip-select) and translated between the system domain (e.g., two chip-select signals) and the physical domain (e.g., four ranks requiring four chip-select signals), effectively presenting a different memory density to the system. Petitioner contended that Klein supplied the missing element of explicit, switch-based load isolation. Klein taught a method for bus capacitance reduction using transfer gates (switches) controlled by a state decoder. This decoder, which could be a programmable logic device, responded to input signals like chip-selects to selectively couple or decouple memory banks from the data bus.
    • Motivation to Combine: A POSITA would combine Klein's bus switching teachings with Amidi's memory module architecture to improve performance. The explicit goal of Klein was to reduce parasitic capacitance and increase memory access speed by isolating unaccessed memory loads. Applying this known technique to the memory ranks in Amidi's module was presented as a predictable design choice to achieve a more efficient and faster memory system.
    • Expectation of Success: The combination involved applying a known switching mechanism (Klein) to a standard memory module architecture (Amidi) to achieve a well-understood benefit (reduced bus loading), leading to a high expectation of success.

Ground 2: Obviousness over Amidi and Wiggers - Claims 15-17, 22, 24, 26, and 31-33 are obvious over Amidi in view of Wiggers.

  • Prior Art Relied Upon: Amidi (Application # 2006/0117152) and Wiggers (Patent 6,011,710).
  • Core Argument for this Ground:
    • Prior Art Mapping: As in the first ground, Petitioner relied on Amidi for the foundational memory module circuit comprising a logic element, register, and PLL, along with the concept of memory domain translation. Petitioner then argued that Wiggers provided an alternative teaching for the load isolation and selective coupling limitations. Wiggers disclosed a memory system with removable modules that used switches, such as FETs, to selectively couple and decouple individual memory devices from the data bus. These switches were shown to be responsive to control signals from a memory controller, directly teaching the functionality of selectively isolating memory device loads from the computer system. The combination of Amidi's rank-multiplying circuit and Wiggers's switch-based load isolation was argued to render the challenged claims obvious.
    • Motivation to Combine: A POSITA would be motivated to integrate the switching method taught by Wiggers into Amidi's memory module for the same reasons as with Klein: to improve performance by isolating memory device loads. Wiggers explicitly taught using switches to decouple memory devices to improve signal integrity on the data bus. A POSITA would see this as a beneficial and logical addition to Amidi's module, which aimed to increase memory capacity, to ensure the increased capacity did not degrade performance due to higher bus capacitance.
    • Expectation of Success: Integrating Wiggers's straightforward switching circuitry into Amidi's memory module was a predictable implementation of known electrical engineering principles with a clear and expected outcome of improved performance.

4. Key Claim Construction Positions

  • translate: Petitioner argued this term, based on its construction in a reexamination of a related patent, required a circuit configurable to convert address and/or control signals between a system memory domain and a physical memory domain. This construction was central to mapping Amidi's CPLD function, which converted two system-side chip-selects into four physical-side rank-selects.
  • logic element: Citing a related reexamination, Petitioner asserted this term should be construed as an element that performs a logic function or comprises a logic circuit. This broad construction allowed Amidi's CPLD, Klein's state decoder, and Wiggers's FET switches to satisfy the limitation.
  • selectively isolating / coupling: Petitioner implicitly argued these terms were met by the teachings in Klein and Wiggers of using electronic switches (transfer gates or FETs) to physically connect or disconnect memory devices from a common data bus in response to control signals. This function was key to overcoming the primary reference, Amidi.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 15-17, 22, 24, 26, and 31-33 of the ’150 patent as unpatentable under 35 U.S.C. §103.