Diablo Technologies Inc v. Netlist Inc

1. Case Identification

• Case #: IPR2014-00883
• Patent #: 8,081,536
• Filed: June 21, 2014
• Petitioner(s): Diablo Technologies, Inc.
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 1, 16, 17, 24, 30, and 31

2. Patent Overview

• Title: Circuit For Memory Module
• Brief Description: The ’536 patent describes a circuit for a memory module used in a computer system. The technology enables a module with a first, larger number of memory ranks to be controlled by a memory controller that outputs a second, smaller number of chip-select signals by using the on-module circuit to decode the controller signals and generate the larger number of internal chip-select signals needed to access the ranks, thereby selectively isolating the electrical load of unselected ranks.

3. Grounds for Unpatentability

Ground 1: Obviousness over Klein and Amidi - Claims 1, 16, 17, 24, 30, and 31 are obvious over Klein in view of Amidi.

• Prior Art Relied Upon: Klein (Application # 2001/0008006) and Amidi (Application # 2006/0117152).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Klein taught a memory module with a circuit that reduces bus capacitance by decoupling unaccessed memory banks from a data bus. Amidi was argued to teach a four-rank Double Data Rate (DDR) memory module that emulates a two-rank module for a standard controller. Amidi’s circuit (a CPLD) receives two input chip-select signals and an address signal to generate four output chip-select signals, thereby selecting one rank while isolating the others. Petitioner asserted the combination of Klein’s isolation concept and Amidi’s rank-multiplying architecture met all limitations of independent claim 1. For dependent claim 16, Petitioner argued Amidi's teaching of a Serial Presence Detect (SPD) device, which stores data to make the four-rank module appear as a two-rank module, satisfied the limitation of characterizing the module with attributes different from its actual attributes.
  • Motivation to Combine: A POSITA would combine Klein’s bus switching technique with Amidi’s memory module architecture to gain the known benefit of isolating memory device loads from the computer system, which reduces parasitic capacitance and increases the speed of memory access.
  • Expectation of Success: Petitioner asserted that combining a known isolation technique with a known memory module design to achieve predictable improvements in performance would have been a straightforward design choice with a high expectation of success.

Ground 2: Obviousness over Ludwig and Amidi - Claims 1, 16, 17, 24, 30, and 31 are obvious over Ludwig in view of Amidi.

• Prior Art Relied Upon: Ludwig (Patent 5,581,498) and Amidi (Application # 2006/0117152).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Ludwig disclosed a stacked-chip memory module with a dedicated interface chip (VIC chip) that functions as the claimed circuit. Ludwig’s VIC chip receives a small number of input signals (address lines and a single chip-enable signal) and generates four distinct output chip-enable signals to select one of four memory layers (ranks), while isolating the non-selected layers. Petitioner then argued that Amidi supplied the necessary teachings for modernizing Ludwig’s architecture, such as the use of DDR memory circuits, a phase-locked loop (PLL) for clock signals, and an SPD device for storing emulated module attributes to satisfy the dependent claims.
  • Motivation to Combine: A POSITA would combine these references as they both address the problem of increasing memory density while maintaining compatibility with existing memory controllers. It would have been a natural and predictable design evolution to update the fundamental rank-multiplying architecture of Ludwig with the modern DDR memory features and compatibility mechanisms disclosed in Amidi.
  • Expectation of Success: Petitioner contended that applying modern, standardized memory features from Amidi to the established, conceptually similar architecture of Ludwig would be a predictable task for a skilled artisan.

Ground 3: Obviousness over Klein, Amidi, and Dell - Claims 16, 17, 30, and 31 are obvious over Klein in view of Amidi and Dell.

• Prior Art Relied Upon: Klein (Application # 2001/0008006), Amidi (Application # 2006/0117152), and Dell (Patent 6,446,184).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground augmented the Klein/Amidi combination, arguing that Dell remedied any perceived deficiency in teaching the limitations of dependent claim 16. Petitioner asserted Dell explicitly taught a memory module with a presence detect (PD) system that uses both non-volatile memory for initial PD data and volatile memory for modified PD data. This system allows a module with actual attributes (e.g., four banks) to work with a computer system expecting different attributes (e.g., two banks) by writing modified data. This was argued to be a direct teaching of storing data that characterizes the module with attributes different from its actual physical attributes.
  • Motivation to Combine: A POSITA would be motivated to incorporate Dell’s advanced method for managing and modifying PD data into the Amidi/Klein module to achieve improved and more flexible compatibility with various computer systems, a primary goal in memory module design.
  • Expectation of Success: The integration of Dell’s known compatibility-enhancing feature into the combined Amidi/Klein memory module architecture was presented as a predictable implementation.
• Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations including the JEDEC industry standard and other permutations of the primary references (e.g., Amidi in view of Dell), but these relied on similar design modification and combination theories.

4. Key Claim Construction Positions

• chip-select: Petitioner cited a construction from a related reexamination, based on an IEEE dictionary definition, stating "chip select" is a logical function that gates inputs and outputs and clarifies that address signals are not ordinarily considered chip-select signals without specific disclosure.
• rank: Citing a related reexamination, Petitioner argued a "rank" is a block or area of memory chips on a module where all individual memories within the rank are typically connected by the same chip-select signal.

5. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1, 16, 17, 24, 30, and 31 as unpatentable under 35 U.S.C. §103.