PTAB

IPR2014-00982

SanDisk Corp v. Netlist Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Data Transfer Scheme for Non-Volatile Memory Module
  • Brief Description: The ’187 patent describes a memory system and method for transferring data from a volatile memory subsystem to a non-volatile memory subsystem. The method involves transferring smaller portions of a data word into a buffer and then transferring the entire data word from the buffer to the non-volatile memory.

3. Grounds for Unpatentability

Ground 1: Anticipation over Park '251 - Claims 1-2, 6, 10-11, 15, 19-20, 24, 26-27, and 31 are anticipated by Park '251.

  • Prior Art Relied Upon: Park ‘251 (Patent 7,467,251).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Park ’251 discloses every limitation of the challenged independent claims. Park ’251 describes a flash memory apparatus with a volatile SRAM buffer memory (the "volatile memory subsystem") and a non-volatile flash memory. Data is transferred by loading two 16-bit portions of a 32-bit data word from two temporary storage units into a buffering multiplexer (the "buffer"), which then transfers the aggregated 32-bit data word to the non-volatile memory. This process directly maps to the ’187 patent's method of transferring smaller portions (16-bit) into a buffer before transferring the entire data word (32-bit). Petitioner asserted that the bitwidth of Park '251's combined temporary storage units (32 bits) is equal to the bitwidth of the data word, meeting another key limitation.

Ground 2: Obviousness over Park '251 and Poechmueller - Claims 3, 12, 21, and 28 are obvious over Park '251 in view of Poechmueller.

  • Prior Art Relied Upon: Park ‘251 (Patent 7,467,251) and Poechmueller (Application # 2005/0060488).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the anticipation argument using Park ’251 as the primary reference. Dependent claim 3 adds the limitation that an inactivated segment of the volatile memory conducts a "self-refresh." Petitioner argued that Poechmueller discloses a dynamic random access memory (DRAM) system that performs self-refresh operations on portions of memory in a low-power sleep mode.
    • Motivation to Combine: A POSITA would combine Park ’251 with Poechmueller because both relate to hybrid memory systems. Petitioner argued a POSITA would be motivated to replace the SRAM in Park ’251 with the self-refreshing DRAM from Poechmueller to gain known advantages, such as greater memory capacity and lower power consumption, which was a well-known design choice.
    • Expectation of Success: The petition implied a high expectation of success, as using DRAM with self-refresh capabilities in hybrid memory systems was conventional at the time of the invention.

Ground 3: Obviousness over Park '273 and Lee - Claims 1, 6-10, 15-19, 24-26, 31, and 32 are obvious over Park '273 in view of Lee.

  • Prior Art Relied Upon: Park ‘273 (Application # 2005/0141273) and Lee (Application # 2003/0158995).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Park ’273 discloses a flash memory system with a buffer memory (volatile subsystem) that transfers data in units of sectors (portions) to a random data input/output circuit (buffer), which then outputs data in units of pages (entire data words) to the non-volatile flash memory. This meets the core claim limitations. Lee was introduced to explicitly teach that the volatile memory subsystem can have a bitwidth equal to the bitwidth of the entire data word (page), a detail Petitioner argued was not explicitly disclosed in Park ’273.
    • Motivation to Combine: A POSITA would combine these references because both relate to DRAM-based memory systems. A POSITA would supplement the system of Park ’273 with Lee's teachings on page-mode DRAM access to improve memory throughput, a known benefit of Lee’s architecture. This would involve arranging the DRAM of Park ’273 into pages as taught by Lee.
    • Expectation of Success: Petitioner argued success would be expected, as utilizing page-mode DRAM access to improve throughput was a well-understood and predictable modification.

  • Additional Grounds: Petitioner asserted numerous additional obviousness challenges, including combinations of Park ’251 with Jeddeloh (Patent 5,430,742) to add error-correcting code (ECC) features, and various three- and four-reference combinations building on the core teachings of Park ’251, Park ’273, and Lee.

4. Key Claim Construction Positions

  • "bitwidth of the volatile memory subsystem": Petitioner proposed construing this term as “any width of data (e.g., in bits or bytes) that the volatile memory subsystem is capable of processing.” This term was added during prosecution to secure allowance. Petitioner argued that because the term is not defined in the specification and is not a term of art, its meaning should be derived from the specification's examples of various bit and byte widths. This broad construction was central to Petitioner's argument that the prior art met the limitation, as the combined storage capacity of prior art buffer segments could be considered the "bitwidth."

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-32 of the ’187 patent as unpatentable.