Diablo Technologies Inc v. Netlist Inc

1. Case Identification

• Case #: IPR2014-01011
• Patent #: 7,881,150
• Filed: June 22, 2014
• Petitioner(s): Diablo Technologies, Inc.
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 15-17, 22, 24, 26, and 31-33

2. Patent Overview

• Title: Circuit Providing Load Isolation And Memory Domain Translation For Memory Module
• Brief Description: The ’150 patent describes a circuit for a memory module that manages a plurality of memory devices (e.g., DRAMs) arranged in ranks. The circuit uses a logic element to translate signals between the computer system's memory domain and the module's physical memory domain, enabling the system to perceive a memory configuration (e.g., fewer ranks with higher density) different from the physical arrangement, while also isolating electrical loads.

3. Grounds for Unpatentability

Ground 1: Obviousness over Ludwig in view of Amidi - Claims 15-17, 22, 24, 26, and 31-33

• Prior Art Relied Upon: Ludwig (Patent 5,581,498) and Amidi (Application # 2006/0117152).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Ludwig disclosed the core concept of using an interface chip on a stacked memory module to translate signals, effectively making multiple physical memory chips appear as a single, higher-density chip to the host system. Ludwig’s interface chip contained logic elements and responded to input signals (address and chip enable) to selectively couple data lines. However, Ludwig did not explicitly disclose a register or a phase-lock loop (PLL). Amidi was alleged to supply these missing elements, as it taught a modern Double Data Rate (DDR) memory module circuit that explicitly included a logic element (CPLD), a register, and a PLL, all operationally coupled to DDR memory devices.
  • Motivation to Combine: Petitioner asserted that a person of ordinary skill in the art (POSITA) would have been motivated to combine the teachings because both references aimed to solve the same problem: increasing memory module density while maintaining compatibility with existing memory controllers. A POSITA would have naturally looked to a modern DDR memory architecture like Amidi’s to implement Ludwig’s conceptual signal translation, incorporating standard DDR components like a register and a PLL for proper timing and synchronization.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success because incorporating a register and PLL into a memory interface circuit were well-known techniques for ensuring signal integrity and synchronization in high-speed memory systems.

Ground 2: Obviousness over Dell in view of Karabatsos - Claims 15-17, 22, 24, 26, and 31-33

• Prior Art Relied Upon: Dell (Patent 6,446,184) and Karabatsos (Patent 6,446,158).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended that Dell disclosed a memory module with an ASIC (logic element) and a register that performed address re-mapping, allowing a four-bank memory device to be used in a system expecting a two-bank device. This taught the key limitations of translating between system and physical memory domains to achieve a different perceived memory density. Karabatsos was asserted to teach the remaining elements, including the use of a PLL for driving DDR memory chips and FET switches to selectively couple or isolate different memory banks from a common data bus in response to control signals.
  • Motivation to Combine: Petitioner argued a POSITA would combine these references to expand memory capacity without increasing the electrical load on the DRAM controller. Dell provided the address translation framework, while Karabatsos provided the specific high-speed clocking (PLL) and electrical isolation (FET switches) mechanisms needed for an efficient and robust implementation in a modern DDR system.
  • Expectation of Success: Integrating a standard timing component like a PLL from Karabatsos into the memory controller circuit of Dell was presented as a predictable design choice for improving performance.

Ground 3: Obviousness over Wong in view of Karabatsos - Claims 15-17, 22, 24, 26, and 31-33

• Prior Art Relied Upon: Wong (Patent 6,414,868) and Karabatsos (Patent 6,446,158).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued Wong disclosed a memory expansion module with a bank control circuit (a logic element) that received and decoded address signals (RAS, CAS, A13) to select between upper and lower memory banks. This decoding functionality was alleged to meet the claim limitation of translating between a system memory domain and a physical memory domain. As in the previous ground, Karabatsos was relied upon to teach the use of a PLL for providing clock signals to memory banks and a register for latching address and control signals.
  • Motivation to Combine: The motivation was similar to the Dell/Karabatsos ground. Both Wong and Karabatsos described systems with multiple memory banks that direct outputs to a common data bus. A POSITA would have been motivated to combine the timing and isolation techniques from Karabatsos with the bank-switching and decoding system of Wong to create a more capable memory expansion module.
  • Expectation of Success: Adding a PLL and register from Karabatsos to the memory control circuit of Wong would have been a straightforward and predictable modification for a POSITA designing a high-speed DDR memory system.

• Additional Grounds: Petitioner also asserted that claims 22, 24, and 26 are anticipated under 35 U.S.C. §102 by Amidi alone.

4. Key Claim Construction Positions

Petitioner argued for constructions consistent with those adopted during prior inter partes reexaminations of related patents.

• translate: Petitioner argued this term should be construed as "requiring a circuit configurable to convert address and/or control signals between a system memory domain and a physical memory domain." This construction is central to its argument that prior art references performing address re-mapping or decoding meet this limitation.
• logic element: Petitioner adopted the Examiner's prior construction of "an element that performs some kind of logic function or an element that comprises a logic circuit." This broad construction allowed Petitioner to map the limitation onto various components in the prior art, such as ASICs, CPLDs, and decoders.

5. Arguments Regarding Discretionary Denial

• Petitioner noted that several key prior art references (Amidi, Dell, Karabatsos) were cited by the Patent Owner during prosecution of the ’150 patent but were "made of record and not relied upon" by the Examiner for any rejection. Petitioner implicitly argued that because the Examiner did not perform a substantive review of these references, the Board should consider them fully in the IPR. This addresses potential arguments against institution under 35 U.S.C. §325(d).

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 15-17, 22, 24, 26, and 31-33 of the ’150 patent as unpatentable.